ML Apps 

In many tasks, such as those in computer vision, machines have begun to exceed human performance. However, machines have much catching up to do when energy costs are accounted for. If ML systems are to become pervasive in our lives then it is imperative that this energy cost be significantly reduced. The availability of such low-energy realizations of ML systems will enable its deployment on embedded platforms such as biomedical devices, wearables, autonomous vehicles, IoT and many others.


ML in Silicon 

Our group focuses on the design of machine learning systems in nanoscale process technologies operating at the limits of robustness, energy efficiency, decision rate, latency, and form factor. We have a unique communications-inspired approach to the design of machine learning systems in silicon. The communications-inspired approach views a communication receiver as an inference kernel. In doing so, one is able to repurpose communication IC design methodologies developed since the early 90's, many in our group, to design inference systems in silicon.

We have also taken this connection between machine learning and communications to the next (advanced) level by treating the circuit and nanodevice fabric itself as a noisy channel on which to extract information from data. Such low signal-to-noise ratio (SNR) circuit fabrics arise when operating at the limits of energy efficiency, throughput, and form factor. We refer to this approach as Shannon-inspired statistical information processing. Statistical information processing therefore enables one to operate at the fundamental limits of efficiency and robustness exists, much like modern day communication links.

Our approach is described in more detail in this position paper and the accompanying presentation. Much of our research since 2013 is being conducted under the SONIC umbrella.

Research Projects

SIP photo 

Research projects in our group seek to take the systems-to-circuits journey as much as possible. Such a journey begins by developing a good understanding of machine learning algorithms, reformulating these to fit within implementation (computational, memory, energy, latency) constraints, following by mapping such algorithms to realizable architectures, which are then realized via integrated circuit implementations.

Resource-constrained Machine Learning Algorithms

Here we consider the problem of designing learning algorithms with minimal precision, storage and computational requirements, while meeting a guaranteed level of decision-making accuracy. Topics include obtaining minimal precision requirements of the commonly used stochastic gradient descent learning algorithm for commonly employed machine learning systems such as the support vector machines, deep neural networks, and others.

Statistical Error Compensation

Shannon-inspired information processing calls for error compensation of system-level errors caused by low-SNR circuit fabrics operating at the limits of efficiency. Statistical error compensation (SEC) leverages the signal and noise statistics to compensate for high raw error-rates (up to 80%) efficiently, i.e., with logic overheads between 5% to 20%. SEC is based on concepts from statistical inference, signal processing, and machine learning, and therefore, is much more efficient than conventional approaches based on fault-tolerant computing. Here, we investigate new approaches for compensating errors using Shannon (communications) theory.

In-memory and In-sensor Information Processing Platforms

Massive data movement in machine learning systems between storage or sensing subsystems and the digital processor, leads to high energy consumption and a severe througput bottleneck, e.g., the memory-processor bottleneck. In this set of projects, we embed information processing at the data source to drastically reduce data movement. Doing so requires information processing to be implemented in a low-SNR fashion, as storage or sensing fabrics are fundamentally incompatible with the high-SNR computing fabrics. Through a combination of application-level error-tolerance, SEC, and retraining, we strive to design in-memory and in-sensor information processing systems that provide a guaranteed level of decision-making accuracy.

Enabling Beyond CMOS Systems

Can Shannon-inspired information processing help compensate for the intrinsic stochastic behavior of beyond CMOS fabrics, and make these competitive with CMOS? In these projects, we apply SEC to study the robustness, energy efficiency, throughput, and form factor, trade-offs when realizing inference kernels in beyond CMOS fabrics such as spin and graphene. These projects are done in collaboration with device researchers in academia and industry.


We gratefully acknowledge the sponsorship of our research by the National Science Foundation, the Defense Advanced Projects Agency, the Semiconductor Research Corporation, the Gigascale Systems Research Center, the Systems on Nanoscale Information fabriCs (SONIC) Center, Texas Instruments, Micron, IBM, GlobalFoundaries, Intel Corporation, National Semiconductor, Rockwell, Analog Devices, and FutureWei Technologies.