Naresh Shanbhag – Selected Publications

Complete list of publications can be found at Google Scholar page

2023

• SNR-boosted 22nm MRAM-based in-memory computing macro using statistical error compensation
  European Solid-State Circuits Conference (ESSCIRC), September 11-14, 2023
  S. K. Roy, H.-M. Ou, M. G. Gamal, P. Deaville, B. Zhang, N. Verma, P. Hanumolu, and N. R. Shanbhag

• On the robustness of randomized ensembles to adversarial perturbations
  International Conference on Machine Learning (ICML), July 23-29, 2023
  H. Dbouk and N. R. Shanbhag

• Boosting the accuracy of SRAM-based in-memory architectures via maximum likelihood-based error compensation method
  IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), June 4-10, 2023
  H. Kim and N. R. Shanbhag

• Enhancing the accuracy of resistive in-memory architectures using adaptive signal processing
  IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), June 4-10, 2023
  H.-M. Ou and N. R. Shanbhag

• PRIVE:Efficient RRAM programming with chip verification for RRAM-based in-memory computing acceleration
  Design Automation and Test in Europe, April 11-19, 2023
  W. He, J. Meng, S. Gonugondla, S. Yu, N. R. Shanbhag, and J.-S. Seo

2022

• Benchmarking in-memory computing architectures
  IEEE Open Journal of the Solid-State Circuits Society (OJ-SSCS), DOI: 10.1109/OJSSCS.2022.3210152, December 2022
  N. R. Shanbhag and S. K. Roy

• Adversarial vulnerability of randomized ensembles
  International Conference on Machine Learning (ICML), July 17-23, 2022
  H. Dbouk and N. R. Shanbhag

• Fundamental limits on the computational accuracy of resistive crossbar-based in-memory architectures [slides]
  IEEE International Symposium on Circuits and Systems (ISCAS), May-June, 2022
  S. K. Roy, A. D. Patil, and N. R. Shanbhag

• IMPQ: Reduced complexity neural networks via granular precision assignments [slides]
  IEEE Conference on Acoustics, Speech, and Signal Processing (ICASSP), May 2022
  S. K. Gonugondla and N. R. Shanbhag

• Comprehending in-memory computing trends via proper benchmarking (invited) [slides]
  IEEE Custom Integrated Circuits Conference (CICC), April 2022
  N. R. Shanbhag and S. K. Roy

2021

• Generalized depthwise-separable convolutions for adversarially robust and efficient neural networks
  Neural Information Processing Systems (NeurIPS), December 2021 (Spotlight)
  H. Dbouk and N. R. Shanbhag

• Robustifying ell_infty adversarial training to the union of perturbation models
  /arXiv:2105.14710 cs.LG
  A. D. Patil, M. Tuttle, A. G. Schwing, and N. R. Shanbhag

• Optimizing selective resilience for CNN resilience
  IEEE International Symposium on Software Reliability Engineering (ISSRE), October 2021
  A. Mahmoud, S. K. S. Hari, C. W. Fletcher, S. V. Adve, C. Sakr, N. R. Shanbhag, P. Molchanov, M. B. Sullivan, T. Tsai, S. W. Keckler

• Signal processing methods to enhance the energy efficiency of in-memory computing architectures
  IEEE Transactions on Signal Processing,DOI: 10.1109/TSP.2021.3130488, 2021
  C. Sakr and N. R. Shanbhag

• Fundamental limits on energy-delay-accuracy of in-memory architectures in inference applications
  IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, DOI: 10.1109/TCAD.2021.3124757, 2021
  S. K. Gonugondla, C. Sakr, H. Dbouk, and N. R. Shanbhag

• A 0.44uJ/dec, 39.9 us/dec, recurrent attention in-memory processor for keyword spotting
  IEEE Journal of Solid-State Circuits (JSSC), July 2021
  H. Dbouk, S. K. Gonugondla, C. Sakr, and N. R. Shanbhag

2020

• Deep in-memory architectures in SRAM: An analog approach to approximate computing (invited)
  Proceedings of the IEEE, December 2020
  M. Kang, S. K. Gonugondla, and N. R. Shanbhag

• SWIPE: Enhancing robustness of ReRAM crossbars for in-memory computing
  IEEE Conference on Computer-Aided Design (ICCAD), November 2020
  S. K. Gonugondla, A. D. Patil, and N. R. Shanbhag

• Fundamental limits on the precision of in-memory architectures (invited)
  IEEE Conference on Computer-Aided Design (ICCAD), November 2020
  S. K. Gonugondla, C. Sakr, H. Dbouk, and N. R. Shanbhag

• DBQ: A differentiable branch quantizer for lightweight deep neural networks
  European Conference on Computer Vision (ECCV), July 2020
  H. Dbouk, H. Sanghvi, M. Mehendale, and N. Shanbhag

• Nanotechnology-inspired information processing systems of the future
  A Computing Community Consortium Workshop Report, May 2020
  R. Bryant, M. Hill, T. Kazior, D. Lee, J. Liu, K. Nahrstedt, V. Narayanan, J. Rabaey, H. Siegelmann, N. Shanbhag, N. Verma, H.-S.P. Wong

• Low-complexity fixed-point convolutional neural networks for automatic target recognition [slides]
  IEEE Conference on Acoustics Speech and Signal Processing (ICASSP), April 2020
  H. Dbouk, H. Geng, C. M. Vineyard, and N. R. Shanbhag

• KeyRAM: A 0.34uJ/decision 18k decisions/s recurrent attention in-memory processor for keyword spotting [slides]
  IEEE Custom Integrated Circuits Conference (CICC), March 2020
  H. Dbouk, S. K. Gonugondla, C. Sakr, and N. R. Shanbhag

• Deep in-memory architectures for machine learning - accuracy versus efficiency trade-offs
  IEEE Transactions on Circuits and Systems I (TCAS), January 2020
  M. Kang, Y. Kim, A. D. Patil, and N. R. Shanbhag

2019

• An energy-efficient programmable mixed-signal accelerator for machine learning algorithms
  IEEE MICRO, Oct. 2019
  M. Kang, P. Srivastava, V. Adve, N. Kim, N. R. Shanbhag

• An energy-efficient classifier via boosted spin channel networks [slides] [Best Paper Award - Honorable Mention]
  IEEE International Symposium on Circuits and Systems (ISCAS), May 2019
  A. D. Patil, S. Manupatruni, D. Nikonov, I. A. Young, N. R. Shanbhag

• An MRAM-based deep in-memory architecture for deep neural networks [slides]
  IEEE International Symposium on Circuits and Systems (ISCAS), May 2019
  A. D. Patil, H. Hua, S. Gonugondla, M. Kang, N. R. Shanbhag

• Minimum precision requirements of general hyperplane classifiers
  IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS), June 2019
  C. Sakr, Y. Kim, and N. R. Shanbhag

• Efficient local secret sharing for distributed blockchain systems
  IEEE Communications Letters, Feb. 2019
  Y. Kim, R. Raman, Y.-S Kim, L. R. Varshney, N. R. Shanbhag

• Error-resilient spintronics via the Shannon-inspired model of computation
  IEEE Journal on Exploratory Solid-State Computational Devices and Circuits (JxCDC), April 2019
  A. D. Patil, S. Manupatruni, D. Nikonov, I. A. Young, N. R. Shanbhag

• Boosted spin channel networks for energy-efficient inference
  IEEE Journal on Exploratory Solid-State Computational Devices and Circuits (JxCDC), Jan. 2019
  A. D. Patil, S. Manupatruni, D. Nikonov, I. A. Young, N. R. Shanbhag

• Accumulation bit-width scaling for ultra-low precision training of deep networks
  International Conference on Learning Representations (ICLR), May 2019
  C. Sakr, N. Wang, C. Chen, J. Choi, A. Agrawal, N. R. Shanbhag, K. Gopalakrishnan

• Per-tensor fixed-point quantization of the back-propagation algorithm
  International Conference on Learning Representations (ICLR), May 2019
  C. Sakr and N. R. Shanbhag

• Shannon-inspired statistical computing for the nanoscale era
  Proceedings of the IEEE, Jan. 2019
  N. R. Shanbhag, N. Verma, Y. Kim, A. D. Patil, and L. R. Varshney

2018

• A variation-tolerant in-memory machine learning classifier via on-chip training
  IEEE Journal of Solid-State Circuits (JSSC), Nov. 2018
  S. K. Gonugondla, M. Kang, and N. R. Shanbhag

• Minimum precision requirements for deep learning with biomedical datasets
  IEEE Biomedical Circuits and Systems Conference (BioCAS), Oct. 2018
  C. Sakr and N. R. Shanbhag

• Generalized water-filling for source-aware energy-efficient SRAMs
  IEEE Transactions on Communications, Oct. 2018
  Y. Kim, M. Kang, L. R. Varshney, and N. R. Shanbhag

• An in-memory VLSI architecture for convolutional neural networks
  IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS), Sept. 2018
  M. Kang, S. Lim, S. K. Gonugondla, and N. R. Shanbhag

• SRAM bit-line swings optimization using generalized waterfilling
  IEEE International Symposium on Information Theory (ISIT), June 2018
  Y. Kim, M. Kang, L. R. Varshney, and N. R. Shanbhag

• PROMISE: An end-to-end design of a programmable mixed-signal accelerator for machine learning algorithms
  IEEE/ACM International Symposium on Computer Architecture (ISCA), June 2018
  P. Srivastava, M. Kang, S. K. Gonugondla, S. Lim, J. Choi, V. Adve, N. S. Kim, and N. R. Shanbhag

• A 19.4 nJ/decision, 364K decisions/s, in-memory random forest multi-class inference accelerator
  IEEE Journal of Solid-State Circuits (JSSC), May 2018
  M. Kang, S. K. Gonugondla, S. Lim, and N. R. Shanbhag

• Energy-efficient deep in-memory architecture for NAND flash memories [slides] [Student Paper Award - Neural Systems and Applications]
  IEEE International Symposium on Circuits and Systems (ISCAS), May 2018
  S. K. Gonugondla, M. Kang, Y. Kim, M. Helm, S. Eilert, and N. R. Shanbhag

• An analytical method to determine minimum per-layer precision of deep neural networks [slides]
  IEEE Conference on Acoustics Speech and Signal Processing (ICASSP), April 2018
  C. Sakr and N. R. Shanbhag

• True gradient-based training of deep binary activated neural networks via continuous binarization [slides]
  IEEE Conference on Acoustics Speech and Signal Processing (ICASSP), April 2018
  C. Sakr, J. Choi, Z. Wang, K. Gopalakrishnan, and N. R. Shanbhag

• Systems on Nanoscale Information fabriCs
  Government Microcircuit Applications & Critical Technology (GOMACTech) Conference, March 2018
  N. R. Shanbhag, Y. Kim, A. Singer, B. Murmann, N. Verma, J. Rabaey, and D. Blaauw

• A 42 pJ/decision 3.12 TOPS/W robust in-memory machine learning classifier with on-chip training [slides]
  International Solid-State Circuits Conference (ISSCC), Feb 2018
  S. K. Gonugondla, M. Kang, and N. R. Shanbhag

• A rank decomposed statistical error compensation technique for robust convolutional neural networks in the near threshold voltage regime
  Journal of Signal Processing Systems, Feb 2018
  Y. Lin, S. Zhang, and N. R. Shanbhag

• A multi-functional in-memory inference processor using a standard 6T SRAM array
  IEEE Journal of Solid-State Circuits (JSSC), January 2018
  M. Kang, S. K. Gonugondla, A. D. Patil, and N. R. Shanbhag

2017

• A 19.4 nJ/decision 364K decisions/s in-memory random forest classifier in 6T SRAM array [slides]
  43rd European Solid-State Circuits Conference (ESSCIRC), September 2017
  M. Kang, S. K. Gonugondla, and N. R. Shanbhag

• Analytical guarantees on numerical precision of deep neural networks [slides] [code]
  International Conference on Machine Learning (ICML), August 2017
  C. Sakr, Y. Kim, and N. R. Shanbhag

• Invited: A systems approach to computing in beyond CMOS fabrics [slides]
  Design Automation Conference (DAC), June 2017
  A. D. Patil, N. R. Shanbhag, L. R. Varshney, E. Pop, H.-S. P. Wong, S. Mitra, J. Rabaey, J. Weldon, L. Pileggi, S. Manipatruni, D. Nikonov, and I. A. Young

• PredictiveNet: An energy-efficient convolutional neural network via zero prediction
  IEEE International Symposium on Circuits and Systems (ISCAS), May 2017
  Y. Lin, C. Sakr, Y. Kim, and N. R. Shanbhag

• Minimum precision requirements for the SVM-SGD learning algorithm [slides]
  IEEE Conference on Acoustics Speech and Signal Processing (ICASSP), March 2017
  C. Sakr, A. D. Patil, S. Zhang, Y. Kim, and N. R. Shanbhag

• Slicer architectures for analog-to-information conversion in channel equalizers
  IEEE Transactions on Communications, March 2017
  A. Wadhwa, U. Madhow, and N. R. Shanbhag

• Shannon-inspired statistical computing to enable spintronics
  arxiv:1702.06119, February 2017
  A. D. Patil, S. Manipatruni, D. Nikonov, I. A. Young, and N. R. Shanbhag

2016

• A 481pJ/decision 3.4M decisions/s multifunctional deep in-memory inference processor using standard 6T SRAM array
  arxiv:1610.07501, October 2016
  M. Kang, S. Gonugondla, A. D. Patil, N. R. Shanbhag

• Variation-tolerant architectures for convolutional neural networks in the near threshold voltage regime
  IEEE International Workshop on Signal Processing Systems (SiPS), August 2016
  Y. Lin, S. Zhang and N. R. Shanbhag

• In-memory computing architectures for sparse distributed memory
  IEEE Transactions on Biomedical Circuits and Systems, August 2016
  M. Kang and N. R. Shanbhag

• Embedded Algorithmic Noise-Tolerance for signal processing and machine learning systems via data path decomposition
  IEEE Transactions on Signal Processing, July 2016
  S. Zhang and N. R. Shanbhag

• Error resilient and energy efficient MRF message passing based stereo image matching
  IEEE Transactions on VLSI, March 2016
  E. Kim, J. Choi, N. R. Shanbhag, and R. Rutenbar

• A study of BER-optimal ADC-based receiver for serial links
  IEEE Transactions On Circuits and Systems97I, May 2016
  Y. Lin, M.-S. Keel, A. Faust, A. Xu, N. R. Shanbhag, E. Rosenbaum, and A. Singer

• Machine learning in silicon 96 A communications-inspired approach [slides]
  International Conference on Machine Learning (ICML), 2016
  N. R. Shanbhag

• Perfect error compensation via algorithmic error cancellation [slides]
  IEEE Conference on Acoustics Speech and Signal Processing (ICASSP), 2016
  S. K. Gonugondla, B. Shim and N. R. Shanbhag

• Analysis of error resiliency of belief propagation in computer vision
  IEEE Conference on Acoustics Speech and Signal Processing (ICASSP), 2016
  J. Choi, A. D. Patil, R. Rutenbar, and N. R. Shanbhag

• Probabilistic error models for machine learning kernels implemented on stochastic nanoscale fabrics
  Design, Automation and Test in Europe (DATE), 2016
  S. Zhang and N. R. Shanbhag

• Reducing the energy cost of inference via in-sensor information processing
  arXiv:1607.00667, 2016
  S. Zhang, M. Kang, C. Sakr, and N. R. Shanbhag

• Error-resilient machine learning in near threshold voltage via classifier ensemble
  arxiv:1607.00667, 2016
  S. Zhang and N. R. Shanbhag

• Understanding the energy and precision requirements for online learning
  arxiv:1607.00669, 2016
  C. Sakr, A. D. Patil, S. Zhang, and N. R. Shanbhag

• GDOT: a graphene-based nanofunction for dot-product computation
  IEEE Symposium on VLSI Technology, 2016
  N. C. Wang, S. K. Gonugondla, I. Nahlus, N. R. Shanbhag, and E. Pop

2015

• An energy-efficient memory-based high-throughput VLSI architecture for convolutional networks [slides]
  IEEE Conference on Acoustics Speech and Signal Processing (ICASSP), 2015
  M. Kang, S. K. Gonugondla, M.-S. Keel, and N. R. Shanbhag

• Energy-efficient and high throughput sparse distributed memory architecture [slides]
  IEEE International Symposium on Circuits and Systems (ISCAS), 2015
  M. Kang, E. P. Kim, M.-S. Keel, and N. R. Shanbhag

• Reduced overhead error compensation for energy efficient machine learning kernels
  International Conference on Computer Aided Design (ICCAD), 2015
  S. Zhang and N. R. Shanbhag

2014

• Energy-efficient accelerator architecture for stereo image matching using approximate computing and statistical error compensation
  IEEE Global Conference on Signal and Information Processing (GlobalSIP), 2014
  E. P. Kim and N. R. Shanbhag

• Embedded error compensation for energy efficient DSP systems
  IEEE Global Conference on Signal and Information Processing (GlobalSIP), 2014
  S. Zhang and N. R. Shanbhag

• Energy-efficient dot product computation using a switched analog circuit architecture
  International Symposium on Low-Power Electronic Design (ISLPED), 2014
  I. Nahlus, E. P. Kim, N. R. Shanbhag, and D. Blaauw

• Reducing energy at the minimum energy operating point (MEOP) via statistical error compensation
  IEEE Transactions on VLSI, June 2014
  R. A. Abdallah, and N. R. Shanbhag

• Space-time slicer architectures for analog-to-information conversion in channel equalizers
  IEEE International Conference on Communications, June 2014
  A. Wadhwa, M. Madhow, and N. Shanbhag

• An energy-efficient VLSI architecture for pattern recognition via deep embedding of computation in SRAM
  IEEE Conference on Acoustics Speech and Signal Processing (ICASSP) May 2014
  M. Kang, M.-S. Keel, N. Shanbhag, S. Eilert, and K. Curewitz

• A robust message passing based stereo matching kernel via system-level error resiliency
  IEEE Conference on Acoustics Speech and Signal Processing (ICASSP), May 2014
  E. Kim, J. Choi, N. Shanbhag, R. Rutenbar

• A 0.79 pJ/K-gate, 83% efficient unified core and voltage regulator architecture for sub/near-threshold operation in 130nm CMOS
  IEEE Journal of Solid-State Circuits, 2014
  S. Zhang, J. Tu, N. R. Shanbhag, and P. Krein

• System-level optimization of switched-capacitor VRM and Core for sub/near-Vt computing
  IEEE Transactions on Circuits and Systems, 2014
  S. Zhang, N. R. Shanbhag, and P. Krein

• A 3.6-mW 50-MHz PN code acquisition filter via statistical error compensation in 180nm CMOS
  IEEE Transactions on VLSI, April 2014
  E. P. Kim, D. J. Baker, S. P. Narayanan, N. R. Shanbhag, and D. L. Jones

2013

• An energy-efficient ECG processor in 45nm CMOS using statistical error compensation
  IEEE Journal of Solid-State Circuits, November 2013
  R. Abdallah and N. R. Shanbhag

• Error resilient MRF message passing architecture for stereo matching
  IEEE Workshop on Signal Processing Systems October 2013
  J. Choi, E. P. Kim, R. Rutenbar, and N. Shanbhag

• Robust and energy-efficient multimedia systems via likelihood processing
  IEEE Transactions on Multimedia February 2013
  R. Abdallah and N. R. Shanbhag

• Statistical analysis of algorithmic noise-tolerance
  IEEE Conference on Acoustics Speech and Signal Processing (ICASSP) May 2013
  E. P. Kim and N. R. Shanbhag

• Error-resilient systems via statistical signal processing
  IEEE Workshop on Signal Processing Systems (SiPS), October2013
  R. A. Abdallah, and N. Shanbhag

2012

• Soft N-modular redundancy
  IEEE Transactions on Computers, March 2012
  E. Kim and N. R. Shanbhag

• Energy efficient LDPC decoders based on error resiliency
  IEEE Workshop on Signal Processing Systems, October 2012
  E. P. Kim and N. R. Shanbhag

• BER-Optimal Analog-to-Digital converters for communication links
  IEEE Transactions on Signal Processing, July 2012
  R. Narasimha, M. Lu, N. R. Shanbhag, and A. C. Singer

• A sphere decoding approach to the vector Viterbi algorithm
  46th Asilomar Conference on Signals, Systems and Computers, 2012
  P. Kairouz, A. Xu, N. Shanbhag, and A. Singer

• A 14.5 fJ/cycle/k-Gate, 0.33 V ECG Processor in 45 nm CMOS using statistical error compensation
  IEEE Custom Integrated Circuits Conference (CICC) September 2012
  R. A. Abdallah, and N. R. Shanbhag

• FEC-based 4 Gb/s backplane transceiver in 90nm CMOS
  IEEE Custom Integrated Circuits Conference (CICC) September 2012
  A. C. Faust, R. L. Narasimha, K. Bhatia, A. Srivastava, C. Kong, H.-M. Bae, E. Rosenbaum, and N. Shanbhag

• System-driven metrics for the design and adaptation of analog to digital converters
  IEEE Conference on Acoustics Speech and Signal Processing (ICASSP) March 2012
  R. Narasimha, G. Zeitler, N. Shanbhag, A. Singer, and G. Kramer

• A fully automated technique for constructing FSM abstractions of non-ideal latches in communication systems
  IEEE Conference on Acoustics Speech and Signal Processing (ICASSP) March 25-30, 2012
  K. Aadithya, Y. Lin, A. Xu, J. Roychowdhury, and N. Shanbhag

2011

• Low-power and error-resilient PN code acquisition filter via statistical error compensation
  IEEE Custom Integrated Circuits Conference September 2011
  E. P. Kim, S. P. Narayanan, N. R. Shanbhag, and D. L. Jones

• Least squares approximation and polyphase decomposition for pipelining recursive filters
  IEEE Conference on Acoustics Speech and Signal Processing (ICASSP), May 22-27, 2011
  A. Gupta, A. C. Singer, and N. R. Shanbhag

• Energy-efficient high-speed links using BER-optimal ADCs
  IEEE Electrical Design of Advanced Package & Systems Symposium 2011
  Y. Lin, A. Xu, N. R. Shanbhag, A. C. Singer

• System-assisted mixed-signal design
  DATE 2011 (invited)
  N. R. Shanbhag and A. C. Singer

• System energy minimization via joint optimization of the DC-DC converter and the core
  ISLPED 2011
  R. A. Abdallah, P. Shenoy, N. R. Shanbhag, and P. T. Krein

• An energy-efficient multiple-input multiple output (MIMO) detector architecture
  SIPS 2011
  E. P. Kim and N. R. Shanbhag

• Engineering of error statistics for energy-efficient robust digital signal processing systems
  Silicon Errors in Logic: System Effects (SELSE), March 29-30, 2011
  R. A. Abdallah and N. R. Shanbhag

• Timing error statistics for energy-efficient robust DSP systems
  DATE 2011
  R. A. Abdallah, Y.-H. Lee and N. R. Shanbhag

• VLSI architectures for soft-decision decoding of Reed-Solomon codes
  IEEE Transactions on Information Theory, February 2011
  A. Ahmed, R. Koetter, and N. R. Shanbhag

• Overcoming the power wall: Connecting voltage domains in series
  2011 International Conference on Energy Aware Computing (ICEAC), 2011
  P. S. Shenoy, S. Zhang, R. A. Abdallah, P. T. Krein, and N. R. Shanbhag

2010

• Robust and energy-efficient DSP systems via output probability processing
  ICCD 2010
  R. Abdallah and N. R. Shanbhag

• Stochastic computation
  DAC 2010 (invited)
  N. R. Shanbhag, R. Abdallah, R. Kumar, and D. L. Jones

• Minimum energy operation via error-resiliency
  IEEE Embedded Systems Letters, December 2010
  R. A. Abdallah, and N. R. Shanbhag

• The stochastic networked computation
  IEEE Transactions on VLSI, October 2010
  G. Varatkar, S. Narayanan, N. Shanbhag and D. Jones

• Computation as estimation: A general framework for robustness and energy-efficiency in SoCs
  IEEE Transactions on Signal Processing, August 2010
  S. Narayanan, G. Varatkar, D. L. Jones, and N. R. Shanbhag

• BER-aware adaptive ADC-equalizer receiver for communication links
  SiPS 2010
  R. Narasimha, N. R. Shanbhag, and A. C. Singer

• Soft NMR: Analysis and Application to DSP Systems
  IEEE Conference on Acoustics, Speech, and Signal Processing March 2010
  E. Kim and N. R. Shanbhag

• BER-optimal ADCs for Communication Links
  ISCAS 2010
  M. Lu, N. R. Shanbhag, and A. Singer

• Design of energy-efficient high-speed links via forward error-correction (FEC)
  IEEE Transactions on Circuits and Systems-II, May 2010
  R. Narasimha and N. R. Shanbhag

2009

• Error-resilient low-power Viterbi decoder architectures
  IEEE Transactions on Signal Processing, December 2009
  R. Abdallah and N. R. Shanbhag

• DSP-based multimode signaling for FEXT reduction in multi-Gbps links
  EPEPS 2009
  P. Milosevic, J. E. Schutt-Aine, and N. R. Shanbhag

• Impact of DFE Error Propagation in FEC-based high-speed I/O links
  GLOBECOM 2009
  R. L. Narasimha, Nirmal Warke and Naresh Shanbhag

• Energy-efficient performance budgeting in FEC-based high-speed I/O links
  EPEPS 2009
  R. L. Narasimha, and N. R. Shanbhag

• Low-power implementation of a high-throughput LDPC decoder for IEEE 802.11n standard
  SiPS 2009
  J. Cho, N. R. Shanbhag, W. Sung

• Low-power low complexity Viterbi decoder for tail-biting codes in Long Term Evolution
  SiPS 2009
  R. Abdallah, S-J. Lee, M. Goel, and N. R. Shanbhag

• Soft NMR: Exploiting statistics for energy-efficiency
  Int. Symp. on System-on-Chip (SOC) Oct. 2009
  E. Kim, R. Abdallah, and N. R. Shanbhag

2008

• Fast power transient management for OC-192 add/drop networks
  IEEE Journal of Solid-State Circuits, December 2008
  H.-M. Bae, J. B. Ashbrook, N. R. Shanbhag, and A. C. Singer

• Electronic dispersion compensation
  IEEE Signal Processing Magazine, November 2008
  A. Singer, N. Shanbhag and H.-M. Bae

• The search for alternative computational paradigms for the post-silicon era
  IEEE Design and Test of Computers, July/August 2008
  N. Shanbhag, S. Mitra, G. D. Veciana, M. Orshansky, R. Marculescu, J. Roychowdhury, D. Jones, and J. Rabaey

• Error-resilient motion-estimation architecture
  IEEE Transactions on VLSI, October 2008
  G. Varatkar and N. Shanbhag

• Joint equalization and coding for on-chip bus communications
  IEEE Transactions on VLSI, March 2008
  S. Sridhara, G. Balamurugan, and N. R. Shanbhag

• An 11.5 Gb/s MLSE based CDR IC with dynamic power-transient tolerance
  ISSCC 2008
  H.-M. Bae, J. Ashbrook, N. Shanbhag, and A. Singer

• Error-resilient Viterbi decoders via state-clustering
  Proceedings of the 2008 IEEE Workshop on Signal Processing Systems October 8-10, 2008
  R. Abdallah, and N. R. Shanbhag

• Forward error-correction for high-speed IO
  Proceedings of the 42th Annual Asilomar Conference on Signals, Systems, and Computers/ October 26-29, 2008
  R. L. Narasimha, and N. R. Shanbhag

• Error-resilient Viterbi decoders
  Proceedings of the 2008 IEEE International Symposium on Low Power Electronics and Design August 11-13, 2008
  R. Abdallah, and N. R. Shanbhag

• Trends in energy-efficiency and robustness of stochastic sensor NOC
  IEEE Great Lakes Symposium on VLSI May 4-6, 2008
  G. Varatkar, S. P. Narayanan, N. Shanbhag and D. L. Jones

• Variation-tolerant, low-power PN-code acquisition using stochastic sensor NOC
  IEEE International Symposium on Circuits and Systems May 18-21, 2008
  G. Varatkar, S. P. Narayanan, N. Shanbhag and D. L. Jones

• Computation is estimation: Estimation-theoretic IC design improves robustness and reduces power
  Proceedings of IEEE International Conference on Acoustics, Speech and Signal Processing March 30-April 4, 2008
  S. P. Narayanan, G. Varatkar, D. L. Jones, and N. Shanbhag

• Electronic equalization of fiber optic links
  International Zurich Seminar on Communications March 12-14, 2008
  A. C. Singer, N. R. Shanbhag and Hyeon-Min Bae

2007

• Coding for reliable on-chip busses: A class of fundamental bounds and practical codes
  IEEE Transactions on CAD, May 2007
  S. Sridhara and N. R. Shanbhag

• Sensor-Networks-Inspired low-power robust PN code acquisition
  Proceedings of the 41th Annual Asilomar Conference on Signals, Systems, and Computers, November 4-7, 2007
  S. P. Narayanan, G. Varatkar, D. L. Jones, and N. Shanbhag

• Variation-tolerant motion estimation architecture
  IEEE Workshop on Signal Processing Systems (SIPS 2007), October 17-19, 2007
  G. Varatkar, S. P. Narayanan, N. Shanbhag and D. L. Jones

• Sensor network-on-a-chip
  IEEE Symposium on System-on-a-Chip Design Nov. 19-21, 2007
  G. Varatkar, S. P. Narayanan, N. Shanbhag and D. L. Jones

2006

• Dual sampling skewed CMOS design for soft error-tolerance
  IEEE Transactions on CAS II, Dec. 2006
  M. Zhang and N. R. Shanbhag

• Robust sequential element design with built-in soft-error resilience
  IEEE Transactions on VLSI, December 2006]
  M. Zhang, S. Mitra, T. M. Mak, N. Seifert, Q. Shi, K.-S. Kim, N. R. Shanbhag, N. Wang, and S. Patel

• An MLSE receiver for electronic dispersion compensation of OC-192 fiber links
  IEEE Journal of Solid-State Circuits, Nov. 2006
  H.-M. Bae, J. B. Ashbrook, J. Park, N. R. Shanbhag, A. C. Singer, and S. C. Chopra

• Soft error-rate analysis (SERA) methodology
  IEEE Transactions on CAD, Oct. 2006
  M. Zhang and N. R. Shanbhag

• Energy-efficient motion estimation using error-tolerance
  Proceedings of the 2006 International Symposium on Low Power Electronics and Design October 2006
  G. Varatkar and N. R. Shanbhag

• Energy-efficient soft-error tolerant digital signal processing
  IEEE Trans. on VLSI, April 2006
  B. Shim and N. R. Shanbhag

• A 640-Mb/s 2048-bit programmable LDPC decoder chip
  IEEE Journal of Solid-State Circuits, March 2006
  M. Mansour and N. R. Shanbhag

• An MLSE receiver for electronic dispersion compensation of OC-192 fiber links
  ISSCC 2006
  H.-M. Bae, J. Ashbrook, J. Park, N. Shanbhag, A. Singer and S. Chopra

2005

• A 285-MHz MAP decoder in 0.18um CMOS
  IEEE Journal of Solid-State Circuits, August 2005
  S.-J. Lee, Naresh R. Shanbhag, and Andrew C. Singer

• Linear turbo equalization analysis via linearized BER transfer and EXIT charts
  IEEE Tran. Signal Processing, August 2005
  S.-J. Lee, Andrew C. Singer, and Naresh R. Shanbhag

• Area-efficient, high-throughput MAP decoder architectures
  IEEE Trans. on VLSI Systems, August 2005
  S.-J. Lee, N. R. Shanbhag and A. C. Singer

• Coding for system-on-chip networks: A unified framework
  IEEE Transactions on VLSI, June 2005
  S. Sridhara and N. R. Shanbhag

• 8-Gb/s source-synchronous I/O link with adaptive receiver equalization, offset cancellation, and clock de-skew
  IEEE Journal of Solid-State Circuits, January 2005
  J. E. Jaussi, G. Balamurugan, D. R. Johnson, B. Casper, A. Martin, J. Kennedy, N. Shanbhag, R. Mooney

• A novel design methodology for high-performance programmable decoder cores for AA-LDPC codes
  Journal of VLSI Signal Processing, 2005
  M. Mansour and N. R. Shanbhag

• Energy-efficient VLSI architecture for linear turbo equalizer
  Journal of VLSI Signal Processing, 2005
  S.-J. Lee, N. R. Shanbhag and A. C. Singer

• Joint equalization and coding for on-chip bus communication
  International Conference on Quality Electronic Design (ISQED), 2005
  S. Sridhara, G. Balamurugan, and N. R. Shanbhag

• A low-power bus design using joint repeater insertion and coding
  Proceedings of the 2005 International Symposium on Low Power Electronics and Design, August 2005
  S. Sridhara and N. R. Shanbhag

• A CMOS design style for logic circuit hardening
  IEEE International Reliability Physics Symposium Apr. 17-21, 2005
  M. Zhang and N. Shanbhag

• An energy-efficient circuit technique for single event transient noise-tolerance
  IEEE International Symposium on Circuits and Systems May 23-26, 2005
  M. Zhang and N. Shanbhag

• Coding for reliable buses: fundamental limits and practical codes
  IEEE VLSI Design Conference, January, 2005
  S. Sridhara and N. R. Shanbhag

2004

• High-power keeps cool
  IEEE Circuits and Devices Magazine, July-August 2004
  M. Lucas, N. R. Shanbhag, K. Roy, F. Kurdahi and J. Fagan

• Reliable low-power digital signal processing via reduced precision redundancy
  IEEE Trans. on VLSI Systems, May 2004
  B. Shim, S. Sridhara and N. R. Shanbhag

• Reliable and efficient system-on-a-chip design
  IEEE Computer Magazine, March 2004
  N. R. Shanbhag

• A voltage overscaled low-power digital filter IC
  IEEE Journal of Solid-State Circuits, February 2004
  R. Hegde and N. R. Shanbhag

• Receiver adaptation and system characterization of an 8Gbps source-synchronous I/O link using on-die circuits in 0.13um CMOS
  Symposium on VLSI Circuits, 2004
  G. Balamurugan, R. Mooney, and N. R. Shanbhag

• An 8Gb/s source-synchronous IO link with adaptive receiver equalization, offset cancellation, and clock de-skew
  ISSCC/ 2004
  J. Jaussi, G. Balamurugan, D. Johnson, B. Casper, A. Martin, J. Kennedy, R. Mooney, and N. Shanbhag

• Performance analysis of the adaptive parity check matrix based soft-decision decoding algorithm
  Conference Record of the Thirty-Eighth Asilomar Conference on Signals, Systems and Computers, November 2004
  A. Arshad, R. Koetter and N. R. Shanbhag

• A novel forward-backward predictor based low-power DSP system
  IEEE Workshop on Signal Processing Systems (SIPS2004), 2004
  B. Shim and N. R. Shanbhag

• Reduced complexity interpolation for soft-decoding of Reed-Solomon codes
  IEEE International Symposium on Information Theory, June 2004
  A. Arshad, R. Koetter and N. R. Shanbhag

• Switching methods for linear turbo equalization
  IEEE International Symposium on Circuits and Systems, May 2004
  S.-J. Lee, N. R. Shanbhag, and A. C. Singer

• Switching LMS linear turbo equalization
  IEEE International Conference on Acoustics, Speech and Signal Processing, May 2004
  S.-J. Lee, A. C. Singer, and N. R. Shanbhag

• Area and energy efficient crosstalk avoidance codes for on-chip busses
  International Conference on Computer Design, October 11-13, 2004
  S. Sridhara, A. Arshad, and N. R. Shanbhag

• A soft error rate analysis (SERA) methodology
  Proceedings of International Conference on Computer-Aided Design, 2004
  M. Zhang and N. R. Shanbhag

• A communication-theoretic design paradigm for reliable SOCs
  Design Automation Conference, June 2004

• A unified coding framework for networks-on-a-chip
  Design Automation Conference, June 2004 S. Sridhara and N. R. Shanbhag

• VLSI architectures for soft-decoding of Reed-Solomon codes
  International Communications Conference, June 2004 A. Arshad, R. Koetter and N. R. Shanbhag

2003

• High-throughput LDPC decoders
  IEEE Trans. on VLSI Systems, December 2003
  M. Mansour and N. R. Shanbhag

• System design of a low-power IO link
  Proceedings of Asilomar Conference/, Nov. 2003
  S.-J. Lee and N. R. Shanbhag

• Analysis of linear turbo equalizer via EXIT chart
  Proc. of Global Telecommunication Conference, Dec. 2003
  S.-J. Lee, A. C. Singer, and N. R. Shanbhag

• Energy-efficient soft error-tolerant digital signal processing
  Proceedings of 37th Annual Asilomar Conference on Signals, Systems, and Computers, Nov. 2003
  B. Shim, N. Shanbhag and S.-J. Lee

• Modeling and mitigation of jitter in multi-gbps source-synchronous IO links
  Proceedings of the 21st International Conference on Computer Design/, Oct. 13-15, 2003
  G. Balamurugan and N. R. Shanbhag

• Modeling of jitter in high-speed inter-chip communication systems
  Proceedings of the 37th Annual Asilomar Conference on Signals, Systems, and Computers, Nov. 2003 G. Balamurugan and N. R. Shanbhag

• A low-power VLSI architecture for SISO decoding
  Proceedings of the 2003 International Symposium on Low Power Electronics and Design, August 2003
  M. M. Mansour and N. R. Shanbhag

• A novel design methodology for programmable decoder cores for AA-LDPC codes
  Proceedings of the 2003 IEEE Workshop on Signal Processing Systems (SIPS ’03), August 2003
  M. M. Mansour and N. R. Shanbhag

• Systolic interpolation architectures for soft decoding of Reed-Solomon codes
  Proceedings of the 2003 IEEE Workshop on Signal Processing Systems (SIPS ’03),August 2003 A. Ahmed, N. R. Shanbhag and R. Koetter

• Area-efficient, High-throughput VLSI architecture for MAP-based turbo equalizer
  Proceedings of the 2003 IEEE Workshop on Signal Processing Systems (SIPS ’03), August 2003 S.-J. Lee, N. R. Shanbhag and A. C. Singer

• Performance analysis of algorithmic noise-tolerance techniques
  Proceedings of the 2003 IEEE International Symposium on Circuits and Systems, May 2003
  B. Shim and N. R. Shanbhag

• High-bandwidth transimpedence amplifier design using active transmission line
  Proceedings of the 2003 IEEE International Symposium on Circuits and Systems, May 2003
  H.-M. Bae and N. R. Shanbhag

• Architecture-aware LDPC codes
  Proceedings of the 2003 IEEE International Symposium on Circuits and Systems, May 2003
  M. M. Mansour and N. R. Shanbhag

• On the architecture-aware structure of LDPC codes from generalized Ramanujan graphs and their decoder architectures
  37th Annual Conference on Information Sciences and Systems (CISS), March 2003
  M. M. Mansour and N. R. Shanbhag

• VLSI architectures for SISO-APP decoders
  IEEE Trans. on VLSI Systems, August 2003
  M. Mansour and N. R. Shanbhag

• Low-power MIMO signal processing
  IEEE Trans. On VLSI, June 2003
  L. Wang and N. R. Shanbhag

• Energy-efficiency bounds for deep submicron VLSI systems in the presence of noise
  IEEE Trans. on VLSI, April 2003
  L. Wang and N. R. Shanbhag

• Low-power filtering via adaptive error-cancellation
  IEEE Trans. on Signal Processing, February 2003
  L. Wang and N. R. Shanbhag

• Complexity analysis of multicarrier and single-carrier systems for very high-speed digital subscriber lines
  IEEE Trans. on Signal Processing, January 2003
  B. Shim and N. R. Shanbhag

2002

• A 130nm 6GHz 256x32b leakage-tolerant register file
  IEEE Journal of Solid-State Circuits, May 2002
  R. K. Krishnamurthy, A. Alvandpour, G. Balamurugan, N. Shanbhag, K. Soumyanath, and S. Borkar

• Turbo decoder architectures for LDPC codes
  GlobeCOM 2002, Taiwan, Nov. 2002
  M. M. Mansour and N. R. Shanbhag

• Construction of LDPC codes from Ramanujan graphs
  36th Annual Conference on Information Sciences and Systems (CISS), March 2002
  M. M. Mansour and N. R. Shanbhag

• Memory-efficient turbo decoder architectures for LDPC codes
  Proceedings of the 2002 IEEE Workshop on Signal Processing Systems (SIPS ’02), 2002
  M. M. Mansour and N. R. Shanbhag

• Low-power turbo equalizer architecture
  Proceedings of the 2002 IEEE Workshop on Signal Processing Systems (SIPS ’02), 2002
  S.-J. Lee, N. R. Shanbhag and A. C. Singer

• Low power VLSI decoder architectures for LDPC codes
  Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002
  M. M. Mansour and N. R. Shanbhag

• Simplified current and delay models for deep submicron CMOS digital circuits
  Proceedings of the 2002 IEEE International Symposium on Circuits and Systems, 2002
  M. M. Mansour and N. R. Shanbhag

• Reliable and energy-efficient digital signal processing
  Proceedings of the 39th Design Automation Conference, 2002
  N. R. Shanbhag

• Design methodology for high-speed iterative decoder architectures
  2002 IEEE International Conference on Acoustics, Speech, and Signal Processing, 2002
  

2001

• Soft digital signal processing
  IEEE Trans. on VLSI Systems, December 2001
  R. Hegde and N. R. Shanbhag

• High-speed architectures for Reed-Solomon decoders
  IEEE Trans. on VLSI Systems, October 2001
  D. Sarwate and N. Shanbhag

• The twin-transistor noise-tolerant dynamic circuit technique
  IEEE Journal of Solid-State Circuits, Feb. 2001
  G. Balamurugan and N. R. Shanbhag

• Total system energy minimization for wireless image transmission
  Journal of VLSI Signal Processing, 2001
  S. Appadwedula, M. Goel, N. R. Shanbhag, D. L. Jones and K. Ramchandran

• Implementation of a Hermitian decoder IC in 0.35um CMOS
  CICC 2001
  J. B. Ashbrook, N.R. Shanbhag, R. Koetter and R.E. Blahut

• A 130nm 6GHz 256x32b leakage-tolerant register file
  Symposium on VLSI Circuits, 2001
  R. K. Krishnamurthy, A. Alvandpour, G. Balamurugan, N. Shanbhag, K. Soumyanath, and S. Borkar

• A low-power digital filter IC via soft DSP
  Proc. of 2001 Custom Integrated Circuits Conference, May 2001
  R. Hegde and N. Shanbhag

• Low-power AEC-based MIMO Signal Processing for Gigabit Ethernet 1000BaseT Transceivers
  Proc. Intl. Symp. on Low-Power Electronic Design, August 2001
  L. Wang and N. R. Shanbhag

• Reduced Precision Redundancy for Low-power Digital Filtering
  Proceedings of the Asilomar Conference, Asilomar, 2001
  B. Shim, and N. R. Shanbhag

• [http:shanbhag.ece.illinois.edupublicationsSrinivasa-WSPS2001.pdf Low-power FFT via reduced precision redundancy Proc. of IEEE Workshop on Signal Processing Systems, Oct. 2001
  S. Sridhara and N. Shanbhag

2000

• An energy-efficient noise-tolerant dynamic circuit technique
  IEEE Trans. on Circuits and Systems, Part II, November 2000
  L. Wang and N. R. Shanbhag

• Towards achieving energy-efficiency in presence of deep submicron noise
  IEEE Trans. on VLSI Systems, August 2000
  R. Hegde and N. R. Shanbhag

• VLSI implementation of a low-power soft DSP filter
  Proc. of IEEE Workshop on Signal Processing Systems October 2000
  R. Hegde and N. Shanbhag

• Low-power signal processing via error cancellation
  Proc. of IEEE Workshop on Signal Processing Systems , Oct. 2000
  L. Wang and N. R. Shanbhag

• Adaptive error-cancellation for low-power digital filtering
  Proceedings of Asilomar Conference on Signals, Systems and Computers, Oct. 2000
  L. Wang and N. R. Shanbhag

• An energy-efficient leakage-tolerant dynamic circuit technique
  Proc. of ASIC00, Sept. 2000
  L. Wang, R. Krishnamurthy and K. Soumyanath

• Reliable low-power design in the presence of deep submicron noise
  Tutorial paper in Intl’ Symposium on Low-Power Electronics and Design, 2000
  N. R. Shanbhag, K. Soumyanath and S. Martin

• Low-power digital filtering via soft DSP
  2000 Proceedings of International Conference on Acoustics, Speech and Signal Processing, June 2000
  R. Hegde and N. R. Shanbhag

• Architecture driven filter transformations
  2000 International Symposium on Circuits and Systems, May 2000
  M. Sharma and N. R. Shanbhag

• Low-power decimation filters for oversampling ADCs via the decorrelating (DECOR) transform
  2000 International Symposium on Circuits and Systems, May 2000
  D. Seo, N. R. Shanbhag, and M. Feng

• Energy-efficiency bounds for noise-tolerant dynamic circuits
  2000 IEEE International Symposium on Circuits and Systems, May 2000
  N. R. Shanbhag and L. Wang

• A noise-tolerant dynamic circuit design technique
  2000 Custom Integrated Circuits Conference, May 2000
  G. Balamurugan and N. R. Shanbhag

1999

• Dynamic algorithm transforms (DAT): A Systematic approach to low- power reconfigurable signal processing
  IEEE Trans. on VLSI Systems, Dec. 1999
  M. Goel and N. R. Shanbhag

• Dynamic algorithm transforms for low-power reconfigurable adaptive equalizers
  IEEE Trans. on Signal Processing, Oct. 1999
  M. Goel and N. R. Shanbhag

• A low-power reconfigurable adaptive equalizer architecture
  Proceedings of Asilomar Conference on Signals, Systems and Computers, Oct. 1999
  J. Tschanz and N. R. Shanbhag

• Low-power CDMA multiuser receiver architectures
  Proc. of IEEE Workshop on Signal Processing Systems, Oct. 1999
  T. Long and N. R. Shanbhag

• A low-power multimedia communication system for indoor wireless applications
  Proc. of IEEE Workshop on Signal Processing Systems, Oct. 1999
  M. Goel, S. Appadwedula, N. R. Shanbhag, K. Ramchandran, and D. L. Jones

• A low power data-adaptive motion estimation algorithm
  IEEE Workshop on Multimedia Signal Processing 1999
  J. Minocha and N. R. Shanbhag

• Information-theoretic bounds on average signal transition activity
  IEEE Trans. on VLSI Systems, Sept. 1999
  S. Ramprasad, N. R. Shanbhag, and I. N. Hajj

• Signal coding for low power: Fundamental limits and practical realizations
  IEEE Trans. on Circuits and Systems Part II, July 1999
  S. Ramprasad, N. R. Shanbhag, and I. N. Hajj

• Energy-efficient signal processing via algorithmic noise-tolerance
  ISLPED 1999
  R. Hegde and N. R. Shanbhag

• Decorrelating (DECOR) transformations for low-power digital filters
  IEEE Trans. on Circuits and Systems-Part II, June 1999
  S. Ramprasad, N. R. Shanbhag, and I. N. Hajj

• A coding framework for low-power address and data busses
  IEEE Trans. on VLSI Systems, June 1999
  S. Ramprasad, N. R. Shanbhag, and I. N. Hajj

• Energy-efficient dynamic circuit design in the presence of crosstalk noise
  Proc. of Intl. Symp. on Low-Power Electronic Design, 1999
  G. Balamurugan and N. R. Shanbhag

• Lower bounds on energy dissipation and noise-tolerance for deep submicron VLSI
  Proceedings of IEEE International Symposium on Circuits and Systems, June 1999
  R. Hegde and N. R. Shanbhag

• Noise-tolerant dynamic circuit design
  Proceedings of IEEE International Symposium on Circuits and Systems, June 1999
  L. Wang and N. R. Shanbhag

• Low-power distributed arithmetic architectures using non-uniform memory partitioning
  Proceedings of IEEE International Symposium on Circuits and Systems, June 1999
  S. Ramprasad, N. R. Shanbhag, and I. N. Hajj

• Low-power channel coding via dynamic reconfiguration
  Proceedings of International Conference on Acoustics, Speech and Signal Processing, March 1999
  M. Goel and N. R. Shanbhag

• Analytical expressions for power dissipation of macro-blocks in DSP architectures
  VLSI99, 1999
  S. Bobba, I. N. Hajj, and N. R. Shanbhag

• A low-power phase-splitting adaptive equalizer architecture for high bit-rate communication systems
  IEEE Trans. on Signal Processing, March 1999
  R. Hegde and N. R. Shanbhag

1998

• Algorithms transformation techniques for low-power wireless VLSI systems design
  International Journal of Wireless Information Networks, 1998
  N. R. Shanbhag

• A pipelined adaptive NEXT canceller
  IEEE Trans. On Signal Processing, August 1998
  G.-H. Im and N. R. Shanbhag

• Finite-precision analysis of the pipelined strength-reduced adaptive filter
  IEEE Trans. On Signal Processing, June 1998
  M. Goel and N. R. Shanbhag

• VLSI Systems Design of 51.84 Mbs Transceivers for ATM-LAN and Broadband Access
  IEEE Trans. On Signal Processing/, May 1998
  N. R. Shanbhag and G.-H. Im

• Energy-efficiency in the presence of deep submicron noise
  ICCAD98, 1998
  R. Hegde and N. R. Shanbhag

• Efficient wireless image transmission under total power constraint
  IEEE Workshop on Multimedia Signal Processing, 1998
  S. Appadwedula, M. Goel, D. L. Jones, K. Ramchandran, and N. R. Shanbhag

• Low-power digital signal processing via dynamic algorithm transformations (DAT)
  Proceedings of Asilomar Conference on Signals, Systems and Computers, November, 1998
  M. Goel and N. R. Shanbhag

• Low-power equalizers for 51.84 Mbs very high-speed digital subscriber loop (VDSL) modems
  Proc. of IEEE Workshop on Signal Processing Systems/, Oct. 1998
  M. Goel and N. R. Shanbhag

• Decorrelating (DECOR) transformations for low-power adaptive filters
  Proc. of Intl. Symp. on Low-Power Electronic Design, August 1998
  S. Ramprasad, N. R. Shanbhag, and I. N. Hajj

• Low-power reconfigurable signal processing via dynamic algorithm transformations (DAT)
  Proceedings of International Conference on Acoustics, Speech and Signal Processing, May 1998
  M. Goel and N. R. Shanbhag

• A Low-power VLSI design methodology for high bit-rate data communications over UTP Channel
  Proceedings of IEEE International Symposium on Circuits and Systems, June 1998
  M. Goel and N. R. Shanbhag

• Improving the throughput of flexible-precision DSPs via algorithm transformation
  ICASSP98, 1998
  M. Aggarwal, N. Shanbhag, N. Ahuja

• Signal coding for low power: Fundamental limits and practical realizations
  ISCAS 98, 1998
  S. Ramprasad, N. R. Shanbhag, and I. N. Hajj

• Analytical expressions for average bit statistics of signal lines in DSP architectures
  ISCAS98, 1998
  S. Bobba, I. N. Hajj and N. R. Shanbhag

• Coding for low-power address and data busses: A source-coding framework and applications
  1998 Int. Conf. on VLSI Design, January 1998
  S. Ramprasad, N. R. Shanbhag, and I. N. Hajj

1997

• A mathematical basis for power-reduction in digital VLSI systems
  IEEE Trans. on Circuits and Systems, Part II, Nov. 1997
  N. R. Shanbhag

• A low-power phase-splitting adaptive equalizer for high bit-rate communications systems
  IEEE Trans. on Signal Processing, Nov. 1997
  R. Hegde and N. R. Shanbhag

• A pipelined strength-reduced adaptive filter : Finite-precision analysis and application to 155.52 Mbs ATM-LAN
  1997 Proc. Midwest Symposium on Circuits and Systems/, August 1997
  M. Goel and N. R. Shanbhag

• Analytical estimation of signal transition activity from word-level statistics
  IEEE Trans. on CAD, July 1997
  S. Ramprasad, N. R. Shanbhag, and I. N. Hajj

• Low-power adaptive filter architectures and their application to 51.84 Mbs ATM-LAN
  IEEE Trans. on Signal Processing/, May 1997
  N. R. Shanbhag and M. Goel

• Achievable bounds on signal transition activity
  ICCAD97, 1997
  S. Ramprasad, N. R. Shanbhag, and I. N. Hajj

• Dynamic algorithm transformations (DAT) for low-power adaptive signal processing
  Proc. of Intl. Symp. on Low-Power Electronic Design, August 1997
  M. Goel and N. R. Shanbhag

• Analytical estimation of transition activity from word-level signal statistics
  1997 Design Automation Conference, 1997
  S. Ramprasad, N. R. Shanbhag, and I. N. Hajj

• Analytical Estimation of Transition Activity of DSP Architectures
  IEEE International Symposium on Circuits and Systems, June 1997
  S. Ramprasad, N. R. Shanbhag, and I. N. Hajj

• VLSI Systems Design for 51.84 Mbs ATM-LAN
  Proc. IEEE Intl. Symp. on Circuits and Systems/, June 1997
  G.-H. Im and N. R. Shanbhag

• Performance of the strength-reduced adaptive filter architecture for 51.84 Mbs ATM-LAN
  Proc. IEEE Intl. Symp. on Circuits and Systems/, June 1997
  M. Goel and N. R. Shanbhag

1996

• Pipelined adaptive IIR filter architectures using scattered and relaxed look-ahead transformations
  IEEE Trans. on Signal Processing, July 1996
  N. R. Shanbhag and G.-H. Im

• A fundamental basis for power-reduction in VLSI circuits
  ISCAS 1996
  N. R. Shanbhag

• Low-power adaptive filter architectures via strength reduction
  Proc. IEEE Symp. on Low Power Electronics Design, August 1996
  M. Goel and N. R. Shanbhag

• Lower bounds on Power-Dissipation for DSP algorithms
  Proc. IEEE Symp. on Low Power Electronics Design, August 1996
  N. R. Shanbhag

1995

• Pipelined adaptive DFE architectures using relaxed look-ahead
  IEEE Trans. on Signal Processing, June 1995
  N. R. Shanbhag and K. K. Parhi

• Pipelined adaptive IIR filter architecture
  Proc. IEEE Intl. Symp. on Circuits and Systems, April 1995
  N. R. Shanbhag and Gi-Hong Im

1994

• An efficient design verification and test generation methodology
  AT&T Bell Labs. Technical Memorandum, Sept. 1994
  N. R. Shanbhag

• Finite-precision analysis of the pipelined ADPCM coder
  IEEE Trans. on Circuits and Systems, May 1994
  N. R. Shanbhag and K. K. Parhi

• Pipelined architectures for adaptive IIR filters
  AT&T Bell Labs. Technical Memorandum, Sept. 1994
  N. R. Shanbhag and Gi-Hong Im

• A Pipelined VLSI NEXT Canceller for Premises Applications
  AT&T Bell Labs. Technical Memorandum, Feb. 1994
  Gi-Hong Im and N. R. Shanbhag

• A Pipelined VLSI NEXT Canceller for Premises Applications
  Proc. GLOBECOM ’94, 1994
  Gi-Hong Im and N. R. Shanbhag

1993

• Relaxed Look-ahead pipelined LMS adaptive filters and their application to ADPCM coder
  IEEE Trans. on Circuits and Systems, Dec. 1993
  N. R. Shanbhag and K. K. Parhi

• A pipelined adaptive lattice filter architecture
  IEEE Trans. on Signal Processing, May 1993
  N. R. Shanbhag and K. K. Parhi

• A pipelined adaptive differential vector quantizer for low-power speech coding applications
  Proc. IEEE Intl. Symp. on Circuits and Systems, May 1993
  N. R. Shanbhag and K. K. Parhi

• A Pipelined Kalman Filter Architecture
  Proc. 27th Asilomar Conference on Cir., Sys. and Comp., 1993
  N. R. Shanbhag and K. K. Parhi

• Pipelined adaptive quantizers using relaxed look-ahead
  Proc. IEEE Workshop on VLSI in Communications, 1993
  N. R. Shanbhag and K. K. Parhi

• Pipelined adaptive DFE architectures
  SPIE Advanced Signal Processing Algorithms, Architectures, and Implementations IV, July 1993
  N. R. Shanbhag and K. K. Parhi

• A pipelined adaptive differential vector quantizer for low-power speech compression
  Proc. IEEE Intl. Symp. on Circuits and Systems May 1993
  N. R. Shanbhag and K. K. Parhi

• Roundoff error analysis of the pipelined ADPCM coder
  Proc. IEEE Intl. Symp. on Circuits and Systems, May 1993
  N. R. Shanbhag and K. K. Parhi

1992

• Some stability theorems for polygons of polynomials
  IEEE Trans. on Automatic Control, November 1992
  L. R. Pujara and N. R. Shanbhag

• A pipelined adaptive differential vector quantizer for real-time video compression
  Proc. IEEE Workshop on Visual Signal Processing and Communications, Sept. 1992
  N. R. Shanbhag and K. K. Parhi

• A pipelined adaptive lattice filter architecture: Theory and Applications
  Proc. EUSIPCO ’92, Aug. 1992
  N. R. Shanbhag and K. K. Parhi

• A pipelined adaptive lattice filter architecture
  Proc. IEEE Intl. Symp. on Circuits and Systems, May 1992
  N. R. Shanbhag and K. K. Parhi

• A high-speed architecture for ADPCM coder and decoder
  Proc. IEEE Intl. Symp on Circuits and Systems, May 1992
  N. R. Shanbhag and K. K. Parhi

1991

• An improved systolic architecture for 2-D digital filters
  IEEE Trans. on Signal Processing, May 1991
  N. R. Shanbhag

• A single-chip pipelined 2-D FIR filter using residue arithmetic
  IEEE Journal of Solid-State Circuits, May 1991
  N. R. Shanbhag and R. E. Siferd

• A pipelined LMS adaptive filter architecture
  Proc. 25th Asilomar Conf. on Sig., Sys. and Comput, Nov. 1991
  N. R. Shanbhag and K. K. Parhi

• The partition of unstable polygons of polynomials
  Proc. of the American Contr. Conf., June 1991
  L. R. Pujara and N. R. Shanbhag

1990

• Quaternary logic circuits in 2-micro CMOS technology
  IEEE Journal of Solid-State Circuits, June 1990
  N. R. Shanbhag, D. Nagchoudhuri, R. E. Siferd and G. S. Visweswaran

• On the stability of polygons of polynomials with an application : An alternative proof of the edge theorem
  Proc. of the American Contr. Conf., May 1990
  L. R. Pujara and N. R. Shanbhag

• A pipelined systolic 2-D FIR filter using residue arithmetic
  Proceedings of the IEEE National Aerospace and Electronics Conference, May 1990
  N. R. Shanbhag and R. E. Siferd

1989

• On the Stability of Polygon of Polynomials
  Proceedings of the Twenty-Seventh Annual Allerton Conference on Comm., Contr. and Computing, September 1989
  L. R. Pujara and N. R. Shanbhag

1988

• Parallel Implementation of a 4x4-bit multiplier using modified Booth's algorithm
  IEEE Journal of Solid-State Circuits, Aug. 1988
  N. R. Shanbhag and P. Juneja