Naresh Shanbhag – Selected Publications
Complete list of publications can be found at Google Scholar page
2018
2017
A 19.4 nJ/decision 364K decisions/s inmemory random forest classifier in 6T SRAM array [slides]
43rd European SolidState Circuits Conference (ESSCIRC), 2017
M. Kang, S. Gonugondla, N. R. Shanbhag
Analytical guarantees on numerical precision of deep neural networks [slides]
International Conference on Machine Learning (ICML), 2017
Charbel Sakr, Yongjune Kim, and, N. R. Shanbhag
Shannoninspired statistical computing to enable spintronics
arxiv:1702.06119, February 2017
A. D. Patil, S. Manipatruni, D. Nikonov, I. A. Young, and N. R. Shanbhag
Invited: A systems approach to computing in beyond CMOS fabrics [slides]
Design Automation Conference (DAC), June 2017
A. D. Patil, N. R. Shanbhag, L. R. Varshney, E. Pop, H.S. P. Wong, S. Mitra, J. Rabaey, J. Weldon, L. Pileggi, S. Manipatruni, D. Nikonov, and I. A. Young
Minimum precision requirements for the SVMSGD learning algorithm [slides]
IEEE Conference on Acoustics Speech and Signal Processing (ICASSP), 2017
C. Sakr, A. D. Patil, S. Zhang, Y. Kim, and N. R. Shanbhag
Slicer architectures for analogtoinformation conversion in channel equalizers
IEEE Transactions on Communications, March 2017
A. Wadhwa, U. Madhow, N. R. Shanbhag
PredictiveNet: An energyefficient convolutional neural network via zero prediction
IEEE International Symposium on Circuits and Systems (ISCAS), 2017
Y. Lin, C. Sakr, Y. Kim, and N. R. Shanbhag
2016
A 481pJ/decision 3.4M decisions/s multifunctional deep inmemory inference processor using standard 6T SRAM array
arxiv:1610.07501, October 2016
M. Kang, S. Gonugondla, A. D. Patil, N. R. Shanbhag
Variationtolerant architectures for convolutional neural networks in the near threshold voltage regime
IEEE International Workshop on Signal Processing Systems (SiPS), August 2016
Y. Lin, S. Zhang and N. R. Shanbhag
Inmemory computing architectures for sparse distributed memory
IEEE Transactions on Biomedical Circuits and Systems, August 2016
M. Kang and N. R. Shanbhag
Embedded Algorithmic NoiseTolerance for signal processing and machine learning systems via data path decomposition
IEEE Transactions on Signal Processing, July 2016
S. Zhang and N. R. Shanbhag
Error resilient and energy efficient MRF message passing based stereo image matching
IEEE Transactions on VLSI, March 2016
E. Kim, J. Choi, N. R. Shanbhag, and R. Rutenbar
A study of BERoptimal ADCbased receiver for serial links
IEEE Transactions On Circuits and Systems—I, May 2016
Y. Lin, M.S. Keel, A. Faust, A. Xu, N. R. Shanbhag, E. Rosenbaum, and A. Singer
Machine learning in silicon – A communicationsinspired approach [slides]
International Conference on Machine Learning (ICML), 2016
N. R. Shanbhag
Perfect error compensation via algorithmic error cancellation [slides]
IEEE Conference on Acoustics Speech and Signal Processing (ICASSP), 2016
S. K. Gonugondla, B. Shim and N. R. Shanbhag
Analysis of error resiliency of belief propagation in computer vision
IEEE Conference on Acoustics Speech and Signal Processing (ICASSP), 2016
J. Choi, A. D. Patil, R. Rutenbar, and N. R. Shanbhag
Probabilistic error models for machine learning kernels implemented on stochastic nanoscale fabrics
Design, Automation and Test in Europe (DATE), 2016
S. Zhang and N. R. Shanbhag
Reducing the energy cost of inference via insensor information processing
arXiv:1607.00667, 2016
S. Zhang, M. Kang, C. Sakr, and N. R. Shanbhag
Errorresilient machine learning in near threshold voltage via classifier ensemble
arxiv:1607.00667, 2016
S. Zhang and N. R. Shanbhag
Understanding the energy and precision requirements for online learning
arxiv:1607.00669, 2016
C. Sakr, A. D. Patil, S. Zhang, and N. R. Shanbhag
GDOT: a graphenebased nanofunction for dotproduct computation
IEEE Symposium on VLSI Technology, 2016
N. C. Wang, S. K. Gonugondla, I. Nahlus, N. R. Shanbhag, and E. Pop
2015
2014
Energyefficient accelerator architecture for stereo
image matching using approximate computing and statistical error compensation
IEEE Global Conference on Signal and Information Processing (GlobalSIP), 2014
E. P. Kim and N. R. Shanbhag
Embedded error compensation for energy efficient DSP systems
IEEE Global Conference on Signal and Information Processing (GlobalSIP), 2014
S. Zhang and N. R. Shanbhag
Energyefficient dot product computation using a switched analog circuit architecture
International Symposium on LowPower Electronic Design (ISLPED), 2014
I. Nahlus, E. P. Kim, N. R. Shanbhag, and D. Blaauw
Reducing energy at the minimum energy operating point (MEOP) via statistical error compensation
IEEE Transactions on VLSI, June 2014
R. A. Abdallah, and N. R. Shanbhag
Spacetime slicer architectures for analogtoinformation conversion in channel equalizers
IEEE International Conference on Communications, June 2014
A. Wadhwa, M. Madhow, and N. Shanbhag
An energyefficient VLSI architecture for pattern recognition via deep embedding of computation in SRAM
IEEE Conference on Acoustics Speech and Signal Processing (ICASSP) May 2014
M. Kang, M.S. Keel, N. Shanbhag, S. Eilert, and K. Curewitz
A robust message passing based stereo matching kernel via systemlevel error resiliency
IEEE Conference on Acoustics Speech and Signal Processing (ICASSP), May 2014
E. Kim, J. Choi, N. Shanbhag, R. Rutenbar
A 0.79 pJ/Kgate, 83% efficient unified core and voltage regulator architecture for sub/nearthreshold operation in 130nm CMOS
IEEE Journal of SolidState Circuits, 2014
S. Zhang, J. Tu, N. R. Shanbhag, and P. Krein
Systemlevel optimization of switchedcapacitor VRM and Core for sub/nearVt computing
IEEE Transactions on Circuits and Systems, 2014
S. Zhang, N. R. Shanbhag, and P. Krein
A 3.6mW 50MHz PN code acquisition filter via statistical error compensation in 180nm CMOS
IEEE Transactions on VLSI, April 2014
E. P. Kim, D. J. Baker, S. P. Narayanan, N. R. Shanbhag, and D. L. Jones
2013
2012
Soft Nmodular redundancy
IEEE Transactions on Computers, March 2012
E. Kim and N. R. Shanbhag
Energy efficient LDPC decoders based on error resiliency
IEEE Workshop on Signal Processing Systems, October 2012
E. P. Kim and N. R. Shanbhag
BEROptimal AnalogtoDigital converters for communication links
IEEE Transactions on Signal Processing, July 2012
R. Narasimha, M. Lu, N. R. Shanbhag, and A. C. Singer
A sphere decoding approach to the vector Viterbi algorithm
46th Asilomar Conference on Signals, Systems and Computers, 2012
P. Kairouz, A. Xu, N. Shanbhag, and A. Singer
A 14.5 fJ/cycle/kGate, 0.33 V ECG Processor in 45 nm CMOS Using Statistical Error Compensation
IEEE Custom Integrated Circuits Conference (CICC) September 2012
R. A. Abdallah, and N. R. Shanbhag
FECbased 4 Gb/s Backplane Transceiver in 90nm CMOS
IEEE Custom Integrated Circuits Conference (CICC) September 2012
A. C. Faust, R. L. Narasimha, K. Bhatia, A. Srivastava, C. Kong, H.M. Bae, E. Rosenbaum,
and N. Shanbhag
Systemdriven metrics for the design and adaptation of analog to digital converters
IEEE Conference on Acoustics Speech and Signal Processing (ICASSP) March 2012
R. Narasimha, G. Zeitler, N. Shanbhag, A. Singer, and G. Kramer
A fully automated technique for constructing FSM abstractions of nonideal latches in communication systems
IEEE Conference on Acoustics Speech and Signal Processing (ICASSP) March 2530, 2012
K. Aadithya, Y. Lin, A. Xu, J. Roychowdhury, and N. Shanbhag
2011
Lowpower and errorresilient PN code acquisition filter via statistical error compensation
IEEE Custom Integrated Circuits Conference September 2011
E. P. Kim, S. P. Narayanan, N. R. Shanbhag, and D. L. Jones
Least squares approximation and polyphase decomposition for pipelining recursive filters
IEEE Conference on Acoustics Speech and Signal Processing (ICASSP), May 2227, 2011
A. Gupta, A. C. Singer, and N. R. Shanbhag
Energyefficient highspeed links using BERoptimal ADCs
IEEE Electrical Design of Advanced Package & Systems Symposium 2011
Y. Lin, A. Xu, N. R. Shanbhag, A. C. Singer
Systemassisted mixedsignal design
DATE 2011 (invited)
N. R. Shanbhag and A. C. Singer
System energy minimization via joint optimization of the DCDC converter and
the core
ISLPED 2011
R. A. Abdallah, P. Shenoy, N. R. Shanbhag, and P. T. Krein
An energyefficient multipleinput multiple output (MIMO) detector architecture
SIPS 2011
E. P. Kim and N. R. Shanbhag
Engineering of error statistics for energyefficient robust digital signal processing systems
Silicon Errors in Logic: System Effects (SELSE), March 2930, 2011
R. A. Abdallah and N. R. Shanbhag
Timing error statistics for energyefficient robust DSP systems
DATE 2011
R. A. Abdallah, Y.H. Lee and N. R. Shanbhag
VLSI architectures for softdecision decoding of ReedSolomon codes
IEEE Transactions on Information Theory, February 2011
A. Ahmed, R. Koetter, and N. R. Shanbhag
Overcoming the power wall: Connecting voltage domains in series
2011 International Conference on Energy Aware Computing (ICEAC), 2011
P. S. Shenoy, S. Zhang, R. A. Abdallah, P. T. Krein, and N. R. Shanbhag
2010
Robust and energyefficient DSP systems via output probability processing
ICCD 2010
R. Abdallah and N. R. Shanbhag
Stochastic computation
DAC 2010 (invited)
N. R. Shanbhag, R. Abdallah, R. Kumar, and D. L. Jones
Minimum energy operation via errorresiliency
IEEE Embedded Systems Letters, December 2010
R. A. Abdallah, and N. R. Shanbhag
The stochastic networked computation
IEEE Transactions on VLSI, October 2010
G. Varatkar, S. Narayanan, N. Shanbhag and D. Jones
Computation as estimation: A general framework for robustness and energyefficiency in SoCs
IEEE Transactions on Signal Processing, August 2010
S. Narayanan, G. Varatkar, D. L. Jones, and N. R. Shanbhag
BERaware adaptive ADCequalizer receiver for communication links
SiPS 2010
R. Narasimha, N. R. Shanbhag, and A. C. Singer
Soft NMR: Analysis and Application to DSP Systems
IEEE Conference on Acoustics, Speech, and Signal Processing March 2010
E. Kim and N. R. Shanbhag
BERoptimal ADCs for Communication Links
ISCAS 2010
M. Lu, N. R. Shanbhag, and A. Singer
Design of energyefficient highspeed links via forward errorcorrection (FEC)
IEEE Transactions on Circuits and SystemsII, May 2010
R. Narasimha and N. R. Shanbhag
2009
Errorresilient lowpower Viterbi decoder architectures
IEEE Transactions on Signal Processing, December 2009
R. Abdallah and N. R. Shanbhag
DSPbased multimode signaling for FEXT reduction in multiGbps links
EPEPS 2009
P. Milosevic, J. E. SchuttAine, and N. R. Shanbhag
Impact of DFE Error Propagation in FECbased highspeed I/O links
GLOBECOM 2009
R. L. Narasimha, Nirmal Warke and Naresh Shanbhag
Energyefficient performance budgeting in FECbased highspeed I/O links
EPEPS 2009
R. L. Narasimha, and N. R. Shanbhag
Lowpower implementation of a highthroughput LDPC decoder for IEEE 802.11n standard
SiPS 2009
J. Cho, N. R. Shanbhag, W. Sung
Lowpower low complexity Viterbi decoder for tailbiting codes in Long Term Evolution
SiPS 2009
R. Abdallah, SJ. Lee, M. Goel, and N. R. Shanbhag
Soft NMR: Exploiting statistics for energyefficiency
Int. Symp. on SystemonChip (SOC) Oct. 2009
E. Kim, R. Abdallah, and N. R. Shanbhag
2008
Fast power transient management for OC192 add/drop networks
IEEE Journal of SolidState Circuits, December 2008
H.M. Bae, J. B. Ashbrook, N. R. Shanbhag, and A. C. Singer
Electronic dispersion compensation
IEEE Signal Processing Magazine, November 2008
A. Singer, N. Shanbhag and H.M. Bae
The search for alternative computational paradigms for the postsilicon era
IEEE Design and Test of Computers, July/August 2008
N. Shanbhag, S. Mitra, G. D. Veciana, M. Orshansky, R. Marculescu, J. Roychowdhury, D. Jones, and J. Rabaey
Errorresilient motionestimation architecture
IEEE Transactions on VLSI, October 2008
G. Varatkar and N. Shanbhag
Joint equalization and coding for onchip bus communications
IEEE Transactions on VLSI, March 2008
S. Sridhara, G. Balamurugan, and N. R. Shanbhag
An 11.5 Gb/s MLSE based CDR IC with dynamic powertransient tolerance
ISSCC 2008
H.M. Bae, J. Ashbrook, N. Shanbhag, and A. Singer
Errorresilient Viterbi decoders via stateclustering
Proceedings of the 2008 IEEE Workshop on Signal Processing Systems October 810, 2008
R. Abdallah, and N. R. Shanbhag
Forward errorcorrection for highspeed IO
Proceedings of the 42th Annual Asilomar Conference on Signals, Systems, and Computers/ October 2629, 2008
R. L. Narasimha, and N. R. Shanbhag
Errorresilient Viterbi decoders
Proceedings of the 2008 IEEE International Symposium on Low Power Electronics and Design August 1113, 2008
R. Abdallah, and N. R. Shanbhag
Trends in energyefficiency and robustness of stochastic sensor NOC
IEEE Great Lakes Symposium on VLSI May 46, 2008
G. Varatkar, S. P. Narayanan, N. Shanbhag and D. L. Jones
Variationtolerant, lowpower PNcode acquisition using stochastic sensor NOC
IEEE International Symposium on Circuits and Systems May 1821, 2008
G. Varatkar, S. P. Narayanan, N. Shanbhag and D. L. Jones
Computation is estimation: Estimationtheoretic IC design improves robustness and reduces power
Proceedings of IEEE International Conference on Acoustics, Speech and Signal Processing March 30April 4, 2008
S. P. Narayanan, G. Varatkar, D. L. Jones, and N. Shanbhag
Electronic equalization of fiber optic links
International Zurich Seminar on Communications March 1214, 2008
A. C. Singer, N. R. Shanbhag and HyeonMin Bae
2007
Coding for reliable onchip busses: A class of fundamental bounds and practical codes
IEEE Transactions on CAD, May 2007
S. Sridhara and N. R. Shanbhag
SensorNetworksInspired lowpower robust PN code acquisition
Proceedings of the 41th Annual Asilomar Conference on Signals, Systems, and Computers, November 47, 2007
S. P. Narayanan, G. Varatkar, D. L. Jones, and N. Shanbhag
Variationtolerant motion estimation architecture
IEEE Workshop on Signal Processing Systems (SIPS 2007), October 1719, 2007
G. Varatkar, S. P. Narayanan, N. Shanbhag and D. L. Jones
Sensor networkonachip
IEEE Symposium on SystemonaChip Design Nov. 1921, 2007
G. Varatkar, S. P. Narayanan, N. Shanbhag and D. L. Jones
2006
Dual sampling skewed CMOS design for soft errortolerance
IEEE Transactions on CAS II, Dec. 2006
M. Zhang and N. R. Shanbhag
Robust sequential element design with builtin softerror resilience
IEEE Transactions on VLSI, December 2006]
M. Zhang, S. Mitra, T. M. Mak, N. Seifert, Q. Shi, K.S. Kim, N. R. Shanbhag, N. Wang, and S. Patel
An MLSE receiver for electronic dispersion compensation of OC192 fiber links
IEEE Journal of SolidState Circuits, Nov. 2006
H.M. Bae, J. B. Ashbrook, J. Park, N. R. Shanbhag, A. C. Singer, and S. C. Chopra
Soft errorrate analysis (SERA) methodology
IEEE Transactions on CAD, Oct. 2006
M. Zhang and N. R. Shanbhag
Energyefficient motion estimation using errortolerance
Proceedings of the 2006 International Symposium on Low Power Electronics and Design October 2006
G. Varatkar and N. R. Shanbhag
Energyefficient softerror tolerant digital signal processing
IEEE Trans. on VLSI, April 2006
B. Shim and N. R. Shanbhag
A 640Mb/s 2048bit programmable LDPC decoder chip
IEEE Journal of SolidState Circuits, March 2006
M. Mansour and N. R. Shanbhag
An MLSE receiver for electronic dispersion compensation of OC192 fiber links
ISSCC 2006
H.M. Bae, J. Ashbrook, J. Park, N. Shanbhag, A. Singer and S. Chopra
2005
A 285MHz MAP decoder in 0.18um CMOS
IEEE Journal of SolidState Circuits, August 2005
S.J. Lee, Naresh R. Shanbhag, and Andrew C. Singer
Linear turbo equalization analysis via linearized BER transfer and EXIT charts
IEEE Tran. Signal Processing, August 2005
S.J. Lee, Andrew C. Singer, and Naresh R. Shanbhag
Areaefficient, highthroughput MAP decoder architectures
IEEE Trans. on VLSI Systems, August 2005
S.J. Lee, N. R. Shanbhag and A. C. Singer
Coding for systemonchip networks: A unified framework
IEEE Transactions on VLSI, June 2005
S. Sridhara and N. R. Shanbhag
8Gb/s sourcesynchronous I/O link with adaptive receiver equalization, offset cancellation, and clock deskew
IEEE Journal of SolidState Circuits, January 2005
J. E. Jaussi, G. Balamurugan, D. R. Johnson, B. Casper, A. Martin, J. Kennedy, N. Shanbhag, R. Mooney
A novel design methodology for highperformance programmable decoder cores for AALDPC codes
Journal of VLSI Signal Processing, 2005
M. Mansour and N. R. Shanbhag
Energyefficient VLSI architecture for linear turbo equalizer
Journal of VLSI Signal Processing, 2005
S.J. Lee, N. R. Shanbhag and A. C. Singer
Joint equalization and coding for onchip bus communication
International Conference on Quality Electronic Design (ISQED), 2005
S. Sridhara, G. Balamurugan, and N. R. Shanbhag
A lowpower bus design using joint repeater insertion and coding
Proceedings of the 2005 International Symposium on Low Power Electronics and Design, August 2005
S. Sridhara and N. R. Shanbhag
A CMOS design style for logic circuit hardening
IEEE International Reliability Physics Symposium Apr. 1721, 2005
M. Zhang and N. Shanbhag
An energyefficient circuit technique for single event transient noisetolerance
IEEE International Symposium on Circuits and Systems May 2326, 2005
M. Zhang and N. Shanbhag
Coding for reliable buses: fundamental limits and practical codes
IEEE VLSI Design Conference, January, 2005
S. Sridhara and N. R. Shanbhag
2004
Highpower keeps cool
IEEE Circuits and Devices Magazine, JulyAugust 2004
M. Lucas, N. R. Shanbhag, K. Roy, F. Kurdahi and J. Fagan
Reliable lowpower digital signal processing via reduced precision redundancy
IEEE Trans. on VLSI Systems, May 2004
B. Shim, S. Sridhara and N. R. Shanbhag
Reliable and efficient systemonachip design
IEEE Computer Magazine, March 2004
N. R. Shanbhag
A voltage overscaled lowpower digital filter IC
IEEE Journal of SolidState Circuits, February 2004
R. Hegde and N. R. Shanbhag
Receiver adaptation and system characterization of an 8Gbps sourcesynchronous I/O link using ondie circuits in 0.13um CMOS
Symposium on VLSI Circuits, 2004
G. Balamurugan, R. Mooney, and N. R. Shanbhag
An 8Gb/s sourcesynchronous IO link with adaptive receiver equalization, offset cancellation, and clock deskew
ISSCC/ 2004
J. Jaussi, G. Balamurugan, D. Johnson, B. Casper, A. Martin, J. Kennedy, R. Mooney, and N. Shanbhag
Performance analysis of the adaptive parity check matrix based softdecision decoding algorithm
Conference Record of the ThirtyEighth Asilomar Conference on Signals, Systems and Computers, November 2004
A. Arshad, R. Koetter and N. R. Shanbhag
A novel forwardbackward predictor based lowpower DSP system
IEEE Workshop on Signal Processing Systems (SIPS2004), 2004
B. Shim and N. R. Shanbhag
Reduced complexity interpolation for softdecoding of ReedSolomon codes
IEEE International Symposium on Information Theory, June 2004
A. Arshad, R. Koetter and N. R. Shanbhag
Switching methods for linear turbo equalization
IEEE International Symposium on Circuits and Systems, May 2004
S.J. Lee, N. R. Shanbhag, and A. C. Singer
Switching LMS linear turbo equalization
IEEE International Conference on Acoustics, Speech and Signal Processing, May 2004
S.J. Lee, A. C. Singer, and N. R. Shanbhag
Area and energy efficient crosstalk avoidance codes for onchip busses
International Conference on Computer Design, October 1113, 2004
S. Sridhara, A. Arshad, and N. R. Shanbhag
A soft error rate analysis (SERA) methodology
Proceedings of International Conference on ComputerAided Design, 2004
M. Zhang and N. R. Shanbhag
A communicationtheoretic design paradigm for reliable SOCs
Design Automation Conference, June 2004
A unified coding framework for networksonachip
Design Automation Conference, June 2004
S. Sridhara and N. R. Shanbhag
VLSI architectures for softdecoding of ReedSolomon codes
International Communications Conference, June 2004
A. Arshad, R. Koetter and N. R. Shanbhag
2003
Highthroughput LDPC decoders
IEEE Trans. on VLSI Systems, December 2003
M. Mansour and N. R. Shanbhag
System design of a lowpower IO link
Proceedings of Asilomar Conference/, Nov. 2003
S.J. Lee and N. R. Shanbhag
Analysis of linear turbo equalizer via EXIT chart
Proc. of Global Telecommunication Conference, Dec. 2003
S.J. Lee, A. C. Singer, and N. R. Shanbhag
Energyefficient soft errortolerant digital signal processing
Proceedings of 37th Annual Asilomar Conference on Signals, Systems, and Computers, Nov. 2003
B. Shim, N. Shanbhag and S.J. Lee
Modeling and mitigation of jitter in multigbps sourcesynchronous IO links
Proceedings of the 21st International Conference on Computer Design/, Oct. 1315, 2003
G. Balamurugan and N. R. Shanbhag
Modeling of jitter in highspeed interchip communication systems
Proceedings of the 37th Annual Asilomar Conference on Signals, Systems, and Computers, Nov. 2003
G. Balamurugan and N. R. Shanbhag
A lowpower VLSI architecture for SISO decoding
Proceedings of the 2003 International Symposium on Low Power Electronics and Design, August 2003
M. M. Mansour and N. R. Shanbhag
A novel design methodology for programmable decoder cores for AALDPC codes
Proceedings of the 2003 IEEE Workshop on Signal Processing Systems (SIPS ’03), August 2003
M. M. Mansour and N. R. Shanbhag
Systolic interpolation architectures for soft decoding of ReedSolomon codes
Proceedings of the 2003 IEEE Workshop on Signal Processing Systems (SIPS ’03),August 2003
A. Ahmed, N. R. Shanbhag and R. Koetter
Areaefficient, Highthroughput VLSI architecture for MAPbased turbo equalizer
Proceedings of the 2003 IEEE Workshop on Signal Processing Systems (SIPS ’03), August 2003
S.J. Lee, N. R. Shanbhag and A. C. Singer
Performance analysis of algorithmic noisetolerance techniques
Proceedings of the 2003 IEEE International Symposium on Circuits and Systems, May 2003
B. Shim and N. R. Shanbhag
Highbandwidth transimpedence amplifier design using active transmission line
Proceedings of the 2003 IEEE International Symposium on Circuits and Systems, May 2003
H.M. Bae and N. R. Shanbhag
Architectureaware LDPC codes
Proceedings of the 2003 IEEE International Symposium on Circuits and Systems, May 2003
M. M. Mansour and N. R. Shanbhag
On the architectureaware structure of LDPC codes from generalized Ramanujan graphs and their decoder architectures
37th Annual Conference on Information Sciences and Systems (CISS), March 2003
M. M. Mansour and N. R. Shanbhag
VLSI architectures for SISOAPP decoders
IEEE Trans. on VLSI Systems, August 2003
M. Mansour and N. R. Shanbhag
Lowpower MIMO signal processing
IEEE Trans. On VLSI, June 2003
L. Wang and N. R. Shanbhag
Energyefficiency bounds for deep submicron VLSI systems in the presence of noise
IEEE Trans. on VLSI, April 2003
L. Wang and N. R. Shanbhag
Lowpower filtering via adaptive errorcancellation
IEEE Trans. on Signal Processing, February 2003
L. Wang and N. R. Shanbhag
Complexity analysis of multicarrier and singlecarrier systems for very highspeed digital subscriber lines
IEEE Trans. on Signal Processing, January 2003
B. Shim and N. R. Shanbhag
2002
A 130nm 6GHz 256x32b leakagetolerant register file
IEEE Journal of SolidState Circuits, May 2002
R. K. Krishnamurthy, A. Alvandpour, G. Balamurugan, N. Shanbhag, K. Soumyanath, and S. Borkar
Turbo decoder architectures for LDPC codes
GlobeCOM 2002, Taiwan, Nov. 2002
M. M. Mansour and N. R. Shanbhag
Construction of LDPC codes from Ramanujan graphs
36th Annual Conference on Information Sciences and Systems (CISS), March 2002
M. M. Mansour and N. R. Shanbhag
Memoryefficient turbo decoder architectures for LDPC codes
Proceedings of the 2002 IEEE Workshop on Signal Processing Systems (SIPS ’02), 2002
M. M. Mansour and N. R. Shanbhag
Lowpower turbo equalizer architecture
Proceedings of the 2002 IEEE Workshop on Signal Processing Systems (SIPS ’02), 2002
S.J. Lee, N. R. Shanbhag and A. C. Singer
Low power VLSI decoder architectures for LDPC codes
Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002
M. M. Mansour and N. R. Shanbhag
Simplified current and delay models for deep submicron CMOS digital circuits
Proceedings of the 2002 IEEE International Symposium on Circuits and Systems, 2002
M. M. Mansour and N. R. Shanbhag
Reliable and energyefficient digital signal processing
Proceedings of the 39th Design Automation Conference, 2002
N. R. Shanbhag
Design methodology for highspeed iterative decoder architectures
2002 IEEE International Conference on Acoustics, Speech, and Signal Processing, 2002
2001
Soft digital signal processing
IEEE Trans. on VLSI Systems, December 2001
R. Hegde and N. R. Shanbhag
Highspeed architectures for ReedSolomon decoders
IEEE Trans. on VLSI Systems, October 2001
D. Sarwate and N. Shanbhag
The twintransistor noisetolerant dynamic circuit technique
IEEE Journal of SolidState Circuits, Feb. 2001
G. Balamurugan and N. R. Shanbhag
Total system energy minimization for wireless image transmission
Journal of VLSI Signal Processing, 2001
S. Appadwedula, M. Goel, N. R. Shanbhag, D. L. Jones and K. Ramchandran
Implementation of a Hermitian decoder IC in 0.35um CMOS
CICC 2001
J. B. Ashbrook, N.R. Shanbhag, R. Koetter and R.E. Blahut
A 130nm 6GHz 256x32b leakagetolerant register file
Symposium on VLSI Circuits, 2001
R. K. Krishnamurthy, A. Alvandpour, G. Balamurugan, N. Shanbhag, K. Soumyanath, and S. Borkar
A lowpower digital filter IC via soft DSP
Proc. of 2001 Custom Integrated Circuits Conference, May 2001
R. Hegde and N. Shanbhag
Lowpower AECbased MIMO Signal Processing for Gigabit Ethernet 1000BaseT Transceivers
Proc. Intl. Symp. on LowPower Electronic Design, August 2001
L. Wang and N. R. Shanbhag
Reduced Precision Redundancy for Lowpower Digital Filtering
Proceedings of the Asilomar Conference, Asilomar, 2001
B. Shim, and N. R. Shanbhag
[http:shanbhag.ece.illinois.edupublicationsSrinivasaWSPS2001.pdf
Lowpower FFT via reduced precision redundancy
Proc. of IEEE Workshop on Signal Processing Systems, Oct. 2001
S. Sridhara and N. Shanbhag
2000
An energyefficient noisetolerant dynamic circuit technique
IEEE Trans. on Circuits and Systems, Part II, November 2000
L. Wang and N. R. Shanbhag
Towards achieving energyefficiency in presence of deep submicron noise
IEEE Trans. on VLSI Systems, August 2000
R. Hegde and N. R. Shanbhag
VLSI implementation of a lowpower soft DSP filter
Proc. of IEEE Workshop on Signal Processing Systems October 2000
R. Hegde and N. Shanbhag
Lowpower signal processing via error cancellation
Proc. of IEEE Workshop on Signal Processing Systems , Oct. 2000
L. Wang and N. R. Shanbhag
Adaptive errorcancellation for lowpower digital filtering
Proceedings of Asilomar Conference on Signals, Systems and Computers, Oct. 2000
L. Wang and N. R. Shanbhag
An energyefficient leakagetolerant dynamic circuit technique
Proc. of ASIC00, Sept. 2000
L. Wang, R. Krishnamurthy and K. Soumyanath
Reliable lowpower design in the presence of deep submicron noise
Tutorial paper in Intl’ Symposium on LowPower Electronics and Design, 2000
N. R. Shanbhag, K. Soumyanath and S. Martin
Lowpower digital filtering via soft DSP
2000 Proceedings of International Conference on Acoustics, Speech and Signal Processing, June 2000
R. Hegde and N. R. Shanbhag
Architecture driven filter transformations
2000 International Symposium on Circuits and Systems, May 2000
M. Sharma and N. R. Shanbhag
Lowpower decimation filters for oversampling ADCs via the decorrelating (DECOR) transform
2000 International Symposium on Circuits and Systems, May 2000
D. Seo, N. R. Shanbhag, and M. Feng
Energyefficiency bounds for noisetolerant dynamic circuits
2000 IEEE International Symposium on Circuits and Systems, May 2000
N. R. Shanbhag and L. Wang
A noisetolerant dynamic circuit design technique
2000 Custom Integrated Circuits Conference, May 2000
G. Balamurugan and N. R. Shanbhag
1999
Dynamic algorithm transforms (DAT): A Systematic approach to low power reconfigurable signal processing
IEEE Trans. on VLSI Systems, Dec. 1999
M. Goel and N. R. Shanbhag
Dynamic algorithm transforms for lowpower reconfigurable adaptive equalizers
IEEE Trans. on Signal Processing, Oct. 1999
M. Goel and N. R. Shanbhag
A lowpower reconfigurable adaptive equalizer architecture
Proceedings of Asilomar Conference on Signals, Systems and Computers, Oct. 1999
J. Tschanz and N. R. Shanbhag
Lowpower CDMA multiuser receiver architectures
Proc. of IEEE Workshop on Signal Processing Systems, Oct. 1999
T. Long and N. R. Shanbhag
A lowpower multimedia communication system for indoor wireless applications
Proc. of IEEE Workshop on Signal Processing Systems, Oct. 1999
M. Goel, S. Appadwedula, N. R. Shanbhag, K. Ramchandran, and D. L. Jones
A low power dataadaptive motion estimation algorithm
IEEE Workshop on Multimedia Signal Processing 1999
J. Minocha and N. R. Shanbhag
Informationtheoretic bounds on average signal transition activity
IEEE Trans. on VLSI Systems, Sept. 1999
S. Ramprasad, N. R. Shanbhag, and I. N. Hajj
Signal coding for low power: Fundamental limits and practical realizations
IEEE Trans. on Circuits and Systems Part II, July 1999
S. Ramprasad, N. R. Shanbhag, and I. N. Hajj
Energyefficient signal processing via algorithmic noisetolerance
ISLPED 1999
R. Hegde and N. R. Shanbhag
Decorrelating (DECOR) transformations for lowpower digital filters
IEEE Trans. on Circuits and SystemsPart II, June 1999
S. Ramprasad, N. R. Shanbhag, and I. N. Hajj
A coding framework for lowpower address and data busses
IEEE Trans. on VLSI Systems, June 1999
S. Ramprasad, N. R. Shanbhag, and I. N. Hajj
Energyefficient dynamic circuit design in the presence of crosstalk noise
Proc. of Intl. Symp. on LowPower Electronic Design, 1999
G. Balamurugan and N. R. Shanbhag
Lower bounds on energy dissipation and noisetolerance for deep submicron VLSI
Proceedings of IEEE International Symposium on Circuits and Systems, June 1999
R. Hegde and N. R. Shanbhag
Noisetolerant dynamic circuit design
Proceedings of IEEE International Symposium on Circuits and Systems, June 1999
L. Wang and N. R. Shanbhag
Lowpower distributed arithmetic architectures using nonuniform memory partitioning
Proceedings of IEEE International Symposium on Circuits and Systems, June 1999
S. Ramprasad, N. R. Shanbhag, and I. N. Hajj
Lowpower channel coding via dynamic reconfiguration
Proceedings of International Conference on Acoustics, Speech and Signal Processing, March 1999
M. Goel and N. R. Shanbhag
Analytical expressions for power dissipation of macroblocks in DSP architectures
VLSI99, 1999
S. Bobba, I. N. Hajj, and N. R. Shanbhag
A lowpower phasesplitting adaptive equalizer architecture for high bitrate communication systems
IEEE Trans. on Signal Processing, March 1999
R. Hegde and N. R. Shanbhag
1998
Algorithms transformation techniques for lowpower wireless VLSI systems design
International Journal of Wireless Information Networks, 1998
N. R. Shanbhag
A pipelined adaptive NEXT canceller
IEEE Trans. On Signal Processing, August 1998
G.H. Im and N. R. Shanbhag
Finiteprecision analysis of the pipelined strengthreduced adaptive filter
IEEE Trans. On Signal Processing, June 1998
M. Goel and N. R. Shanbhag
VLSI Systems Design of 51.84 Mbs Transceivers for ATMLAN and Broadband Access
IEEE Trans. On Signal Processing/, May 1998
N. R. Shanbhag and G.H. Im
Energyefficiency in the presence of deep submicron noise
ICCAD98, 1998
R. Hegde and N. R. Shanbhag
Efficient wireless image transmission under total power constraint
IEEE Workshop on Multimedia Signal Processing, 1998
S. Appadwedula, M. Goel, D. L. Jones, K. Ramchandran, and N. R. Shanbhag
Lowpower digital signal processing via dynamic algorithm transformations (DAT)
Proceedings of Asilomar Conference on Signals, Systems and Computers, November, 1998
M. Goel and N. R. Shanbhag
Lowpower equalizers for 51.84 Mbs very highspeed digital subscriber loop (VDSL) modems
Proc. of IEEE Workshop on Signal Processing Systems/, Oct. 1998
M. Goel and N. R. Shanbhag
Decorrelating (DECOR) transformations for lowpower adaptive filters
Proc. of Intl. Symp. on LowPower Electronic Design, August 1998
S. Ramprasad, N. R. Shanbhag, and I. N. Hajj
Lowpower reconfigurable signal processing via dynamic algorithm transformations (DAT)
Proceedings of International Conference on Acoustics, Speech and Signal Processing, May 1998
M. Goel and N. R. Shanbhag
A Lowpower VLSI design methodology for high bitrate data communications over UTP Channel
Proceedings of IEEE International Symposium on Circuits and Systems, June 1998
M. Goel and N. R. Shanbhag
Improving the throughput of flexibleprecision DSPs via algorithm transformation
ICASSP98, 1998
M. Aggarwal, N. Shanbhag, N. Ahuja
Signal coding for low power: Fundamental limits and practical realizations
ISCAS 98, 1998
S. Ramprasad, N. R. Shanbhag, and I. N. Hajj
Analytical expressions for average bit statistics of signal lines in DSP architectures
ISCAS98, 1998
S. Bobba, I. N. Hajj and N. R. Shanbhag
Coding for lowpower address and data busses: A sourcecoding framework and applications
1998 Int. Conf. on VLSI Design, January 1998
S. Ramprasad, N. R. Shanbhag, and I. N. Hajj
1997
A mathematical basis for powerreduction in digital VLSI systems
IEEE Trans. on Circuits and Systems, Part II, Nov. 1997
N. R. Shanbhag
A lowpower phasesplitting adaptive equalizer for high bitrate communications systems
IEEE Trans. on Signal Processing, Nov. 1997
R. Hegde and N. R. Shanbhag
A pipelined strengthreduced adaptive filter : Finiteprecision analysis and application to 155.52 Mbs ATMLAN
1997 Proc. Midwest Symposium on Circuits and Systems/, August 1997
M. Goel and N. R. Shanbhag
Analytical estimation of signal transition activity from wordlevel statistics
IEEE Trans. on CAD, July 1997
S. Ramprasad, N. R. Shanbhag, and I. N. Hajj
Lowpower adaptive filter architectures and their application to 51.84 Mbs ATMLAN
IEEE Trans. on Signal Processing/, May 1997
N. R. Shanbhag and M. Goel
Achievable bounds on signal transition activity
ICCAD97, 1997
S. Ramprasad, N. R. Shanbhag, and I. N. Hajj
Dynamic algorithm transformations (DAT) for lowpower adaptive signal processing
Proc. of Intl. Symp. on LowPower Electronic Design, August 1997
M. Goel and N. R. Shanbhag
Analytical estimation of transition activity from wordlevel signal statistics
1997 Design Automation Conference, 1997
S. Ramprasad, N. R. Shanbhag, and I. N. Hajj
Analytical Estimation of Transition Activity of DSP Architectures
IEEE International Symposium on Circuits and Systems, June 1997
S. Ramprasad, N. R. Shanbhag, and I. N. Hajj
VLSI Systems Design for 51.84 Mbs ATMLAN
Proc. IEEE Intl. Symp. on Circuits and Systems/, June 1997
G.H. Im and N. R. Shanbhag
Performance of the strengthreduced adaptive filter architecture for 51.84 Mbs ATMLAN
Proc. IEEE Intl. Symp. on Circuits and Systems/, June 1997
M. Goel and N. R. Shanbhag
1996
1995
1994
1993
Relaxed Lookahead pipelined LMS adaptive filters and their application to ADPCM coder
IEEE Trans. on Circuits and Systems, Dec. 1993
N. R. Shanbhag and K. K. Parhi
A pipelined adaptive lattice filter architecture
IEEE Trans. on Signal Processing, May 1993
N. R. Shanbhag and K. K. Parhi
A pipelined adaptive differential vector quantizer for lowpower speech coding applications
Proc. IEEE Intl. Symp. on Circuits and Systems, May 1993
N. R. Shanbhag and K. K. Parhi
A Pipelined Kalman Filter Architecture
Proc. 27th Asilomar Conference on Cir., Sys. and Comp., 1993
N. R. Shanbhag and K. K. Parhi
Pipelined adaptive quantizers using relaxed lookahead
Proc. IEEE Workshop on VLSI in Communications, 1993
N. R. Shanbhag and K. K. Parhi
Pipelined adaptive DFE architectures
SPIE Advanced Signal Processing Algorithms, Architectures, and Implementations IV, July 1993
N. R. Shanbhag and K. K. Parhi
A pipelined adaptive differential vector quantizer for lowpower speech compression
Proc. IEEE Intl. Symp. on Circuits and Systems May 1993
N. R. Shanbhag and K. K. Parhi
Roundoff error analysis of the pipelined ADPCM coder
Proc. IEEE Intl. Symp. on Circuits and Systems, May 1993
N. R. Shanbhag and K. K. Parhi
1992
1991
1990
1989
1988
