Department of Electrical and Computer Engineering

In-memory computing architectures for sparse distributed memory

*IEEE Transactions on Biomedical Circuits and Systems,*August 2016

M. Kang and N. R. ShanbhagEmbedded Algorithmic Noise-Tolerance for signal processing and machine learning systems via data path decomposition

*IEEE Transactions on Signal Processing,*July 2016

S. Zhang and N. R. ShanbhagError resilient and energy efficient MRF message passing based stereo image matching

*IEEE Transactions on VLSI,*March 2016

E. Kim, J. Choi, N. R. Shanbhag, and R. RutenbarA study of BER-optimal ADC-based receiver for serial links

*IEEE Transactions On Circuits and Systems—I,*May 2016

Y. Lin, M.-S. Keel, A. Faust, A. Xu, N. R. Shanbhag, E. Rosenbaum, and A. SingerMachine learning in Silicon – A Communications-inspired approach

*International Conference on Machine Learning (ICML),*2016

N. R. ShanbhagPerfect error compensation via algorithmic error cancellation

*IEEE Conference on Acoustics Speech and Signal Processing (ICASSP),*2016

S. K. Gonugondla, B. Shim and N. R. ShanbhagAnalysis of error resiliency of belief propagation in computer vision

*IEEE Conference on Acoustics Speech and Signal Processing (ICASSP),*2016

J. Choi, A. Patil, R. Rutenbar, and N. R. ShanbhagProbabilistic error models for machine learning kernels implemented on stochastic nanoscale fabrics

*Design, Automation and Test in Europe (DATE),*2016

S. Zhang and N. R. ShanbhagReducing the energy cost of inference via in-sensor information processing

*arXiv:1607.00667,*2016

S. Zhang, M. Kang, C. Sakr, and N. R. ShanbhagError-resilient machine learning in near threshold voltage via classifier ensemble

*arxiv:1607.00667,*2016

S. Zhang and N. R. ShanbhagUnderstanding the energy and precision requirements for online learning

*arxiv:1607.00669,*2016

C. Sakr, A. Patil, S. Zhang, and N. R. ShanbhagGDOT: a graphene-based nanofunction for dot-product computation

*IEEE Symposium on VLSI Technology,*2016

N. C. Wang, S. K. Gonugondla, I. Nahlus, N. R. Shanbhag, and E. Pop

An energy-efficient memory-based high-throughput VLSI architecture for convolutional networks

*IEEE Conference on Acoustics Speech and Signal Processing (ICASSP),*2015

M. Kang, S. K. Gonugondla, M.-S. Keel, and N. R. ShanbhagEnergy-efficient and High Throughput Sparse Distributed Memory Architecture

*IEEE International Symposium on Circuits and Systems (ISCAS),*2015

M. Kang, E. P. Kim, M.-S. Keel, and N. R. ShanbhagReduced overhead error compensation for energy efficient machine learning kernels

*International Conference on Computer Aided Design (ICCAD),*2015

S. Zhang and N. R. Shanbhag

Energy-efficient accelerator architecture for stereo image matching using approximate computing and statistical error compensation

*IEEE Global Conference on Signal and Information Processing (GlobalSIP),*2014

E. P. Kim and N. R. ShanbhagEmbedded error compensation for energy efficient DSP systems

*IEEE Global Conference on Signal and Information Processing (GlobalSIP),*2014

S. Zhang and N. R. ShanbhagEnergy-efficient dot product computation using a switched analog circuit architecture

*International Symposium on Low-Power Electronic Design (ISLPED),*2014

I. Nahlus, E. P. Kim, N. R. Shanbhag, and D. BlaauwReducing energy at the minimum energy operating point (MEOP) via statistical error compensation

*IEEE Transactions on VLSI,*June 2014

R. A. Abdallah, and N. R. ShanbhagSpace-time slicer architectures for analog-to-information conversion in channel equalizers

*IEEE International Conference on Communications,*June 2014

A. Wadhwa, M. Madhow, and N. ShanbhagAn energy-efficient VLSI architecture for pattern recognition via deep embedding of computation in SRAM

*IEEE Conference on Acoustics Speech and Signal Processing (ICASSP)*May 2014

M. Kang, M.-S. Keel, N. Shanbhag, S. Eilert, and K. CurewitzA robust message passing based stereo matching kernel via system-level error resiliency

*IEEE Conference on Acoustics Speech and Signal Processing (ICASSP),*May 2014

E. Kim, J. Choi, N. Shanbhag, R. RutenbarA 0.79 pJ/K-gate, 83% efficient unified core and voltage regulator architecture for sub/near-threshold operation in 130nm CMOS

*IEEE Journal of Solid-State Circuits,*2014

S. Zhang, J. Tu, N. R. Shanbhag, and P. KreinSystem-level optimization of switched-capacitor VRM and Core for sub/near-Vt computing

*IEEE Transactions on Circuits and Systems,*2014

S. Zhang, N. R. Shanbhag, and P. KreinA 3.6-mW 50-MHz PN code acquisition filter via statistical error compensation in 180nm CMOS

*IEEE Transactions on VLSI,*April 2014

E. P. Kim, D. J. Baker, S. P. Narayanan, N. R. Shanbhag, and D. L. Jones

An energy-efficient ECG processor in 45nm CMOS using statistical error compensation

*IEEE Journal of Solid-State Circuits,*November 2013

R. Abdallah and N. R. ShanbhagError resilient MRF message passing architecture for stereo matching

*IEEE Workshop on Signal Processing Systems*October 2013

J. Choi, E. P. Kim, R. Rutenbar, and N. ShanbhagRobust and energy-efficient multimedia systems via likelihood processing

*IEEE Transactions on Multimedia*February 2013

R. Abdallah and N. R. ShanbhagStatistical analysis of algorithmic noise-tolerance

*IEEE Conference on Acoustics Speech and Signal Processing (ICASSP)*May 2013

E. P. Kim and N. R. ShanbhagError-resilient systems via statistical signal processing

*IEEE Workshop on Signal Processing Systems (SiPS),*October2013

R. A. Abdallah, and N. Shanbhag

Soft N-modular redundancy

*IEEE Transactions on Computers,*March 2012

E. Kim and N. R. ShanbhagEnergy efficient LDPC decoders based on error resiliency

*IEEE Workshop on Signal Processing Systems,*October 2012

E. P. Kim and N. R. ShanbhagBER-Optimal Analog-to-Digital converters for communication links

*IEEE Transactions on Signal Processing,*July 2012

R. Narasimha, M. Lu, N. R. Shanbhag, and A. C. SingerA sphere decoding approach to the vector Viterbi algorithm

*46th Asilomar Conference on Signals, Systems and Computers,*2012

P. Kairouz, A. Xu, N. Shanbhag, and A. SingerA 14.5 fJ/cycle/k-Gate, 0.33 V ECG Processor in 45 nm CMOS Using Statistical Error Compensation

*IEEE Custom Integrated Circuits Conference (CICC)*September 2012

R. A. Abdallah, and N. R. ShanbhagFEC-based 4 Gb/s Backplane Transceiver in 90nm CMOS

*IEEE Custom Integrated Circuits Conference (CICC)*September 2012

A. C. Faust, R. L. Narasimha, K. Bhatia, A. Srivastava, C. Kong, H.-M. Bae, E. Rosenbaum, and N. ShanbhagSystem-driven metrics for the design and adaptation of analog to digital converters

*IEEE Conference on Acoustics Speech and Signal Processing (ICASSP)*March 2012

R. Narasimha, G. Zeitler, N. Shanbhag, A. Singer, and G. KramerA fully automated technique for constructing FSM abstractions of non-ideal latches in communication systems

*IEEE Conference on Acoustics Speech and Signal Processing (ICASSP)*March 25-30, 2012

K. Aadithya, Y. Lin, A. Xu, J. Roychowdhury, and N. Shanbhag

Low-power and error-resilient PN code acquisition filter via statistical error compensation

*IEEE Custom Integrated Circuits Conference*September 2011

E. P. Kim, S. P. Narayanan, N. R. Shanbhag, and D. L. JonesLeast squares approximation and polyphase decomposition for pipelining recursive filters

*IEEE Conference on Acoustics Speech and Signal Processing (ICASSP)*, May 22-27, 2011

A. Gupta, A. C. Singer, and N. R. ShanbhagEnergy-efficient high-speed links using BER-optimal ADCs

*IEEE Electrical Design of Advanced Package & Systems Symposium*2011

Y. Lin, A. Xu, N. R. Shanbhag, A. C. SingerSystem-assisted mixed-signal design

*DATE*2011 (invited)

N. R. Shanbhag and A. C. SingerSystem energy minimization via joint optimization of the DC-DC converter and the core

*ISLPED*2011

R. A. Abdallah, P. Shenoy, N. R. Shanbhag, and P. T. KreinAn energy-efficient multiple-input multiple output (MIMO) detector architecture

*SIPS*2011

E. P. Kim and N. R. ShanbhagEngineering of error statistics for energy-efficient robust digital signal processing systems

*Silicon Errors in Logic: System Effects (SELSE)*, March 29-30, 2011

R. A. Abdallah and N. R. ShanbhagTiming error statistics for energy-efficient robust DSP systems

*DATE*2011

R. A. Abdallah, Y.-H. Lee and N. R. ShanbhagVLSI architectures for soft-decision decoding of Reed-Solomon codes

*IEEE Transactions on Information Theory*, February 2011

A. Ahmed, R. Koetter, and N. R. ShanbhagOvercoming the power wall: Connecting voltage domains in series

*2011 International Conference on Energy Aware Computing (ICEAC)*, 2011

P. S. Shenoy, S. Zhang, R. A. Abdallah, P. T. Krein, and N. R. Shanbhag

Robust and energy-efficient DSP systems via output probability processing

*ICCD*2010

R. Abdallah and N. R. ShanbhagStochastic computation

*DAC*2010 (invited)

N. R. Shanbhag, R. Abdallah, R. Kumar, and D. L. JonesMinimum energy operation via error-resiliency

*IEEE Embedded Systems Letters*, December 2010

R. A. Abdallah, and N. R. ShanbhagThe stochastic networked computation

*IEEE Transactions on VLSI*, October 2010

G. Varatkar, S. Narayanan, N. Shanbhag and D. JonesComputation as estimation: A general framework for robustness and energy-efficiency in SoCs

*IEEE Transactions on Signal Processing*, August 2010

S. Narayanan, G. Varatkar, D. L. Jones, and N. R. ShanbhagBER-aware adaptive ADC-equalizer receiver for communication links

*SiPS*2010

R. Narasimha, N. R. Shanbhag, and A. C. SingerSoft NMR: Analysis and Application to DSP Systems

*IEEE Conference on Acoustics, Speech, and Signal Processing*March 2010

E. Kim and N. R. ShanbhagBER-optimal ADCs for Communication Links

*ISCAS*2010

M. Lu, N. R. Shanbhag, and A. SingerDesign of energy-efficient high-speed links via forward error-correction (FEC)

*IEEE Transactions on Circuits and Systems-II*, May 2010

R. Narasimha and N. R. Shanbhag

Error-resilient low-power Viterbi decoder architectures

*IEEE Transactions on Signal Processing*, December 2009

R. Abdallah and N. R. ShanbhagDSP-based multimode signaling for FEXT reduction in multi-Gbps links

*EPEPS*2009

P. Milosevic, J. E. Schutt-Aine, and N. R. ShanbhagImpact of DFE Error Propagation in FEC-based high-speed I/O links

*GLOBECOM*2009

R. L. Narasimha, Nirmal Warke and Naresh ShanbhagEnergy-efficient performance budgeting in FEC-based high-speed I/O links

*EPEPS*2009

R. L. Narasimha, and N. R. ShanbhagLow-power implementation of a high-throughput LDPC decoder for IEEE 802.11n standard

*SiPS*2009

J. Cho, N. R. Shanbhag, W. SungLow-power low complexity Viterbi decoder for tail-biting codes in Long Term Evolution

*SiPS*2009

R. Abdallah, S-J. Lee, M. Goel, and N. R. ShanbhagSoft NMR: Exploiting statistics for energy-efficiency

*Int. Symp. on System-on-Chip (SOC)*Oct. 2009

E. Kim, R. Abdallah, and N. R. Shanbhag

Fast power transient management for OC-192 add/drop networks

*IEEE Journal of Solid-State Circuits*, December 2008

H.-M. Bae, J. B. Ashbrook, N. R. Shanbhag, and A. C. SingerElectronic dispersion compensation

*IEEE Signal Processing Magazine*, November 2008

A. Singer, N. Shanbhag and H.-M. BaeThe search for alternative computational paradigms for the post-silicon era

*IEEE Design and Test of Computers*, July/August 2008

N. Shanbhag, S. Mitra, G. D. Veciana, M. Orshansky, R. Marculescu, J. Roychowdhury, D. Jones, and J. RabaeyError-resilient motion-estimation architecture

*IEEE Transactions on VLSI*, October 2008

G. Varatkar and N. ShanbhagJoint equalization and coding for on-chip bus communications

*IEEE Transactions on VLSI*, March 2008

S. Sridhara, G. Balamurugan, and N. R. ShanbhagAn 11.5 Gb/s MLSE based CDR IC with dynamic power-transient tolerance

*ISSCC*2008

H.-M. Bae, J. Ashbrook, N. Shanbhag, and A. SingerError-resilient Viterbi decoders via state-clustering

*Proceedings of the 2008 IEEE Workshop on Signal Processing Systems*October 8-10, 2008

R. Abdallah, and N. R. ShanbhagForward error-correction for high-speed I

*O*Proceedings of the 42th Annual Asilomar Conference on Signals, Systems, and Computers/ October 26-29, 2008

R. L. Narasimha, and N. R. ShanbhagError-resilient Viterbi decoders

*Proceedings of the 2008 IEEE International Symposium on Low Power Electronics and Design*August 11-13, 2008

R. Abdallah, and N. R. ShanbhagTrends in energy-efficiency and robustness of stochastic sensor NOC

*IEEE Great Lakes Symposium on VLSI*May 4-6, 2008

G. Varatkar, S. P. Narayanan, N. Shanbhag and D. L. JonesVariation-tolerant, low-power PN-code acquisition using stochastic sensor NOC

*IEEE International Symposium on Circuits and Systems*May 18-21, 2008

G. Varatkar, S. P. Narayanan, N. Shanbhag and D. L. JonesComputation is estimation: Estimation-theoretic IC design improves robustness and reduces power

*Proceedings of IEEE International Conference on Acoustics, Speech and Signal Processing*March 30-April 4, 2008

S. P. Narayanan, G. Varatkar, D. L. Jones, and N. ShanbhagElectronic equalization of fiber optic links

*International Zurich Seminar on Communications*March 12-14, 2008

A. C. Singer, N. R. Shanbhag and Hyeon-Min Bae

Coding for reliable on-chip busses: A class of fundamental bounds and practical codes

*IEEE Transactions on CAD*, May 2007

S. Sridhara and N. R. ShanbhagSensor-Networks-Inspired low-power robust PN code acquisition

*Proceedings of the 41th Annual Asilomar Conference on Signals, Systems, and Computers*, November 4-7, 2007

S. P. Narayanan, G. Varatkar, D. L. Jones, and N. ShanbhagVariation-tolerant motion estimation architecture

*IEEE Workshop on Signal Processing Systems (SIPS 2007)*, October 17-19, 2007

G. Varatkar, S. P. Narayanan, N. Shanbhag and D. L. JonesSensor network-on-a-chip

*IEEE Symposium on System-on-a-Chip Design*Nov. 19-21, 2007

G. Varatkar, S. P. Narayanan, N. Shanbhag and D. L. Jones

Dual sampling skewed CMOS design for soft error-tolerance

*IEEE Transactions on CAS II*, Dec. 2006

M. Zhang and N. R. ShanbhagRobust sequential element design with built-in soft-error resilience

*IEEE Transactions on VLSI*, December 2006]

M. Zhang, S. Mitra, T. M. Mak, N. Seifert, Q. Shi, K.-S. Kim, N. R. Shanbhag, N. Wang, and S. PatelAn MLSE receiver for electronic dispersion compensation of OC-192 fiber links

*IEEE Journal of Solid-State Circuits*, Nov. 2006

H.-M. Bae, J. B. Ashbrook, J. Park, N. R. Shanbhag, A. C. Singer, and S. C. ChopraSoft error-rate analysis (SERA) methodology

*IEEE Transactions on CAD*, Oct. 2006

M. Zhang and N. R. ShanbhagEnergy-efficient motion estimation using error-tolerance

*Proceedings of the 2006 International Symposium on Low Power Electronics and Design*October 2006

G. Varatkar and N. R. ShanbhagEnergy-efficient soft-error tolerant digital signal processing

*IEEE Trans. on VLSI*, April 2006

B. Shim and N. R. ShanbhagA 640-Mb/s 2048-bit programmable LDPC decoder chip

*IEEE Journal of Solid-State Circuits*, March 2006

M. Mansour and N. R. ShanbhagAn MLSE receiver for electronic dispersion compensation of OC-192 fiber links

*ISSCC*2006

H.-M. Bae, J. Ashbrook, J. Park, N. Shanbhag, A. Singer and S. Chopra

A 285-MHz MAP decoder in 0.18um CMOS

*IEEE Journal of Solid-State Circuits*, August 2005

S.-J. Lee, Naresh R. Shanbhag, and Andrew C. SingerLinear turbo equalization analysis via linearized BER transfer and EXIT charts

*IEEE Tran. Signal Processing*, August 2005

S.-J. Lee, Andrew C. Singer, and Naresh R. ShanbhagArea-efficient, high-throughput MAP decoder architectures

*IEEE Trans. on VLSI Systems*, August 2005

S.-J. Lee, N. R. Shanbhag and A. C. SingerCoding for system-on-chip networks: A unified framework

*IEEE Transactions on VLSI*, June 2005

S. Sridhara and N. R. Shanbhag8-Gb/s source-synchronous I/O link with adaptive receiver equalization, offset cancellation, and clock de-skew

*IEEE Journal of Solid-State Circuits*, January 2005

J. E. Jaussi, G. Balamurugan, D. R. Johnson, B. Casper, A. Martin, J. Kennedy, N. Shanbhag, R. MooneyA novel design methodology for high-performance programmable decoder cores for AA-LDPC codes

*Journal of VLSI Signal Processing*, 2005

M. Mansour and N. R. ShanbhagEnergy-efficient VLSI architecture for linear turbo equalizer

*Journal of VLSI Signal Processing*, 2005

S.-J. Lee, N. R. Shanbhag and A. C. SingerJoint equalization and coding for on-chip bus communication

*International Conference on Quality Electronic Design (ISQED)*, 2005

S. Sridhara, G. Balamurugan, and N. R. ShanbhagA low-power bus design using joint repeater insertion and coding

*Proceedings of the 2005 International Symposium on Low Power Electronics and Design*, August 2005

S. Sridhara and N. R. ShanbhagA CMOS design style for logic circuit hardening

*IEEE International Reliability Physics Symposium*Apr. 17-21, 2005

M. Zhang and N. ShanbhagAn energy-efficient circuit technique for single event transient noise-tolerance

*IEEE International Symposium on Circuits and Systems*May 23-26, 2005

M. Zhang and N. ShanbhagCoding for reliable buses: fundamental limits and practical codes

*IEEE VLSI Design Conference*, January, 2005

S. Sridhara and N. R. Shanbhag

High-power keeps cool

*IEEE Circuits and Devices Magazine*, July-August 2004

M. Lucas, N. R. Shanbhag, K. Roy, F. Kurdahi and J. FaganReliable low-power digital signal processing via reduced precision redundancy

*IEEE Trans. on VLSI Systems*, May 2004

B. Shim, S. Sridhara and N. R. ShanbhagReliable and efficient system-on-a-chip design

*IEEE Computer Magazine*, March 2004

N. R. ShanbhagA voltage overscaled low-power digital filter IC

*IEEE Journal of Solid-State Circuits*, February 2004

R. Hegde and N. R. ShanbhagReceiver adaptation and system characterization of an 8Gbps source-synchronous I/O link using on-die circuits in 0.13um CMOS

*Symposium on VLSI Circuits*, 2004

G. Balamurugan, R. Mooney, and N. R. ShanbhagAn 8Gb/s source-synchronous I

*O link with adaptive receiver equalization, offset cancellation, and clock de-skew*ISSCC/ 2004

J. Jaussi, G. Balamurugan, D. Johnson, B. Casper, A. Martin, J. Kennedy, R. Mooney, and N. ShanbhagPerformance analysis of the adaptive parity check matrix based soft-decision decoding algorithm

*Conference Record of the Thirty-Eighth Asilomar Conference on Signals, Systems and Computers*, November 2004

A. Arshad, R. Koetter and N. R. ShanbhagA novel forward-backward predictor based low-power DSP system

*IEEE Workshop on Signal Processing Systems (SIPS2004)*, 2004

B. Shim and N. R. ShanbhagReduced complexity interpolation for soft-decoding of Reed-Solomon codes

*IEEE International Symposium on Information Theory*, June 2004

A. Arshad, R. Koetter and N. R. ShanbhagSwitching methods for linear turbo equalization

*IEEE International Symposium on Circuits and Systems*, May 2004

S.-J. Lee, N. R. Shanbhag, and A. C. SingerSwitching LMS linear turbo equalization

*IEEE International Conference on Acoustics, Speech and Signal Processing*, May 2004

S.-J. Lee, A. C. Singer, and N. R. ShanbhagArea and energy efficient crosstalk avoidance codes for on-chip busses

*International Conference on Computer Design*, October 11-13, 2004

S. Sridhara, A. Arshad, and N. R. ShanbhagA soft error rate analysis (SERA) methodology

*Proceedings of International Conference on Computer-Aided Design*, 2004

M. Zhang and N. R. ShanbhagA communication-theoretic design paradigm for reliable SOCs

*Design Automation Conference*, June 2004A unified coding framework for networks-on-a-chip

*Design Automation Conference*, June 2004 S. Sridhara and N. R. ShanbhagVLSI architectures for soft-decoding of Reed-Solomon codes

*International Communications Conference*, June 2004 A. Arshad, R. Koetter and N. R. Shanbhag

High-throughput LDPC decoders

*IEEE Trans. on VLSI Systems*, December 2003

M. Mansour and N. R. ShanbhagSystem design of a low-power I

*O link*Proceedings of Asilomar Conference/, Nov. 2003

S.-J. Lee and N. R. ShanbhagAnalysis of linear turbo equalizer via EXIT chart

*Proc. of Global Telecommunication Conference*, Dec. 2003

S.-J. Lee, A. C. Singer, and N. R. ShanbhagEnergy-efficient soft error-tolerant digital signal processing

*Proceedings of 37th Annual Asilomar Conference on Signals, Systems, and Computers*, Nov. 2003

B. Shim, N. Shanbhag and S.-J. LeeModeling and mitigation of jitter in multi-gbps source-synchronous I

*O links*Proceedings of the 21st International Conference on Computer Design/, Oct. 13-15, 2003

G. Balamurugan and N. R. ShanbhagModeling of jitter in high-speed inter-chip communication systems

*Proceedings of the 37th Annual Asilomar Conference on Signals, Systems, and Computers*, Nov. 2003 G. Balamurugan and N. R. ShanbhagA low-power VLSI architecture for SISO decoding

*Proceedings of the 2003 International Symposium on Low Power Electronics and Design*, August 2003

M. M. Mansour and N. R. ShanbhagA novel design methodology for programmable decoder cores for AA-LDPC codes

*Proceedings of the 2003 IEEE Workshop on Signal Processing Systems (SIPS ’03)*, August 2003

M. M. Mansour and N. R. ShanbhagSystolic interpolation architectures for soft decoding of Reed-Solomon codes

*Proceedings of the 2003 IEEE Workshop on Signal Processing Systems (SIPS ’03)*,August 2003 A. Ahmed, N. R. Shanbhag and R. KoetterArea-efficient, High-throughput VLSI architecture for MAP-based turbo equalizer

*Proceedings of the 2003 IEEE Workshop on Signal Processing Systems (SIPS ’03)*, August 2003 S.-J. Lee, N. R. Shanbhag and A. C. SingerPerformance analysis of algorithmic noise-tolerance techniques

*Proceedings of the 2003 IEEE International Symposium on Circuits and Systems*, May 2003

B. Shim and N. R. ShanbhagHigh-bandwidth transimpedence amplifier design using active transmission line

*Proceedings of the 2003 IEEE International Symposium on Circuits and Systems*, May 2003

H.-M. Bae and N. R. ShanbhagArchitecture-aware LDPC codes

*Proceedings of the 2003 IEEE International Symposium on Circuits and Systems*, May 2003

M. M. Mansour and N. R. ShanbhagOn the architecture-aware structure of LDPC codes from generalized Ramanujan graphs and their decoder architectures

*37th Annual Conference on Information Sciences and Systems (CISS)*, March 2003

M. M. Mansour and N. R. ShanbhagVLSI architectures for SISO-APP decoders

*IEEE Trans. on VLSI Systems*, August 2003

M. Mansour and N. R. ShanbhagLow-power MIMO signal processing

*IEEE Trans. On VLSI*, June 2003

L. Wang and N. R. ShanbhagEnergy-efficiency bounds for deep submicron VLSI systems in the presence of noise

*IEEE Trans. on VLSI*, April 2003

L. Wang and N. R. ShanbhagLow-power filtering via adaptive error-cancellation

*IEEE Trans. on Signal Processing*, February 2003

L. Wang and N. R. ShanbhagComplexity analysis of multicarrier and single-carrier systems for very high-speed digital subscriber lines

*IEEE Trans. on Signal Processing*, January 2003

B. Shim and N. R. Shanbhag

A 130nm 6GHz 256x32b leakage-tolerant register file

*IEEE Journal of Solid-State Circuits*, May 2002

R. K. Krishnamurthy, A. Alvandpour, G. Balamurugan, N. Shanbhag, K. Soumyanath, and S. BorkarTurbo decoder architectures for LDPC codes

*GlobeCOM 2002, Taiwan*, Nov. 2002

M. M. Mansour and N. R. ShanbhagConstruction of LDPC codes from Ramanujan graphs

*36th Annual Conference on Information Sciences and Systems (CISS)*, March 2002

M. M. Mansour and N. R. ShanbhagMemory-efficient turbo decoder architectures for LDPC codes

*Proceedings of the 2002 IEEE Workshop on Signal Processing Systems (SIPS ’02)*, 2002

M. M. Mansour and N. R. ShanbhagLow-power turbo equalizer architecture

*Proceedings of the 2002 IEEE Workshop on Signal Processing Systems (SIPS ’02)*, 2002

S.-J. Lee, N. R. Shanbhag and A. C. SingerLow power VLSI decoder architectures for LDPC codes

*Proceedings of the 2002 International Symposium on Low Power Electronics and Design*, 2002

M. M. Mansour and N. R. ShanbhagSimplified current and delay models for deep submicron CMOS digital circuits

*Proceedings of the 2002 IEEE International Symposium on Circuits and Systems*, 2002

M. M. Mansour and N. R. ShanbhagReliable and energy-efficient digital signal processing

*Proceedings of the 39th Design Automation Conference*, 2002

N. R. ShanbhagDesign methodology for high-speed iterative decoder architectures

*2002 IEEE International Conference on Acoustics, Speech, and Signal Processing*, 2002

Soft digital signal processing

*IEEE Trans. on VLSI Systems*, December 2001

R. Hegde and N. R. ShanbhagHigh-speed architectures for Reed-Solomon decoders

*IEEE Trans. on VLSI Systems*, October 2001

D. Sarwate and N. ShanbhagThe twin-transistor noise-tolerant dynamic circuit technique

*IEEE Journal of Solid-State Circuits*, Feb. 2001

G. Balamurugan and N. R. ShanbhagTotal system energy minimization for wireless image transmission

*Journal of VLSI Signal Processing*, 2001

S. Appadwedula, M. Goel, N. R. Shanbhag, D. L. Jones and K. RamchandranImplementation of a Hermitian decoder IC in 0.35um CMOS

*CICC*2001

J. B. Ashbrook, N.R. Shanbhag, R. Koetter and R.E. BlahutA 130nm 6GHz 256x32b leakage-tolerant register file

*Symposium on VLSI Circuits*, 2001

R. K. Krishnamurthy, A. Alvandpour, G. Balamurugan, N. Shanbhag, K. Soumyanath, and S. BorkarA low-power digital filter IC via soft DSP

*Proc. of 2001 Custom Integrated Circuits Conference*, May 2001

R. Hegde and N. ShanbhagLow-power AEC-based MIMO Signal Processing for Gigabit Ethernet 1000BaseT Transceivers

*Proc. Intl. Symp. on Low-Power Electronic Design*, August 2001

L. Wang and N. R. ShanbhagReduced Precision Redundancy for Low-power Digital Filtering

*Proceedings of the Asilomar Conference, Asilomar*, 2001

B. Shim, and N. R. Shanbhag[http:shanbhag.ece.illinois.edu

*publications*Srinivasa-WSPS2001.pdf Low-power FFT via reduced precision redundancy*Proc. of IEEE Workshop on Signal Processing Systems*, Oct. 2001

S. Sridhara and N. Shanbhag

An energy-efficient noise-tolerant dynamic circuit technique

*IEEE Trans. on Circuits and Systems, Part II*, November 2000

L. Wang and N. R. ShanbhagTowards achieving energy-efficiency in presence of deep submicron noise

*IEEE Trans. on VLSI Systems*, August 2000

R. Hegde and N. R. ShanbhagVLSI implementation of a low-power soft DSP filter

*Proc. of IEEE Workshop on Signal Processing Systems*October 2000

R. Hegde and N. ShanbhagLow-power signal processing via error cancellation

*Proc. of IEEE Workshop on Signal Processing Systems*, Oct. 2000

L. Wang and N. R. ShanbhagAdaptive error-cancellation for low-power digital filtering

*Proceedings of Asilomar Conference on Signals, Systems and Computers*, Oct. 2000

L. Wang and N. R. ShanbhagAn energy-efficient leakage-tolerant dynamic circuit technique

*Proc. of ASIC00*, Sept. 2000

L. Wang, R. Krishnamurthy and K. SoumyanathReliable low-power design in the presence of deep submicron noise

*Tutorial paper in Intl’ Symposium on Low-Power Electronics and Design*, 2000

N. R. Shanbhag, K. Soumyanath and S. MartinLow-power digital filtering via soft DSP

*2000 Proceedings of International Conference on Acoustics, Speech and Signal Processing*, June 2000

R. Hegde and N. R. ShanbhagArchitecture driven filter transformations

*2000 International Symposium on Circuits and Systems*, May 2000

M. Sharma and N. R. ShanbhagLow-power decimation filters for oversampling ADCs via the decorrelating (DECOR) transform

*2000 International Symposium on Circuits and Systems*, May 2000

D. Seo, N. R. Shanbhag, and M. FengEnergy-efficiency bounds for noise-tolerant dynamic circuits

*2000 IEEE International Symposium on Circuits and Systems*, May 2000

N. R. Shanbhag and L. WangA noise-tolerant dynamic circuit design technique

*2000 Custom Integrated Circuits Conference*, May 2000

G. Balamurugan and N. R. Shanbhag

Dynamic algorithm transforms (DAT): A Systematic approach to low- power reconfigurable signal processing

*IEEE Trans. on VLSI Systems*, Dec. 1999

M. Goel and N. R. ShanbhagDynamic algorithm transforms for low-power reconfigurable adaptive equalizers

*IEEE Trans. on Signal Processing*, Oct. 1999

M. Goel and N. R. ShanbhagA low-power reconfigurable adaptive equalizer architecture

*Proceedings of Asilomar Conference on Signals, Systems and Computers*, Oct. 1999

J. Tschanz and N. R. ShanbhagLow-power CDMA multiuser receiver architectures

*Proc. of IEEE Workshop on Signal Processing Systems*, Oct. 1999

T. Long and N. R. ShanbhagA low-power multimedia communication system for indoor wireless applications

*Proc. of IEEE Workshop on Signal Processing Systems*, Oct. 1999

M. Goel, S. Appadwedula, N. R. Shanbhag, K. Ramchandran, and D. L. JonesA low power data-adaptive motion estimation algorithm

*IEEE Workshop on Multimedia Signal Processing*1999

J. Minocha and N. R. ShanbhagInformation-theoretic bounds on average signal transition activity

*IEEE Trans. on VLSI Systems*, Sept. 1999

S. Ramprasad, N. R. Shanbhag, and I. N. HajjSignal coding for low power: Fundamental limits and practical realizations

*IEEE Trans. on Circuits and Systems Part II*, July 1999

S. Ramprasad, N. R. Shanbhag, and I. N. HajjEnergy-efficient signal processing via algorithmic noise-tolerance

*ISLPED*1999

R. Hegde and N. R. ShanbhagDecorrelating (DECOR) transformations for low-power digital filters

*IEEE Trans. on Circuits and Systems-Part II*, June 1999

S. Ramprasad, N. R. Shanbhag, and I. N. HajjA coding framework for low-power address and data busses

*IEEE Trans. on VLSI Systems*, June 1999

S. Ramprasad, N. R. Shanbhag, and I. N. HajjEnergy-efficient dynamic circuit design in the presence of crosstalk noise

*Proc. of Intl. Symp. on Low-Power Electronic Design*, 1999

G. Balamurugan and N. R. ShanbhagLower bounds on energy dissipation and noise-tolerance for deep submicron VLSI

*Proceedings of IEEE International Symposium on Circuits and Systems*, June 1999

R. Hegde and N. R. ShanbhagNoise-tolerant dynamic circuit design

*Proceedings of IEEE International Symposium on Circuits and Systems*, June 1999

L. Wang and N. R. ShanbhagLow-power distributed arithmetic architectures using non-uniform memory partitioning

*Proceedings of IEEE International Symposium on Circuits and Systems*, June 1999

S. Ramprasad, N. R. Shanbhag, and I. N. HajjLow-power channel coding via dynamic reconfiguration

*Proceedings of International Conference on Acoustics, Speech and Signal Processing*, March 1999

M. Goel and N. R. ShanbhagAnalytical expressions for power dissipation of macro-blocks in DSP architectures

*VLSI99*, 1999

S. Bobba, I. N. Hajj, and N. R. ShanbhagA low-power phase-splitting adaptive equalizer architecture for high bit-rate communication systems

*IEEE Trans. on Signal Processing*, March 1999

R. Hegde and N. R. Shanbhag

Algorithms transformation techniques for low-power wireless VLSI systems design

*International Journal of Wireless Information Networks*, 1998

N. R. ShanbhagA pipelined adaptive NEXT canceller

*IEEE Trans. On Signal Processing*, August 1998

G.-H. Im and N. R. ShanbhagFinite-precision analysis of the pipelined strength-reduced adaptive filter

*IEEE Trans. On Signal Processing*, June 1998

M. Goel and N. R. ShanbhagVLSI Systems Design of 51.84 Mb

*s Transceivers for ATM-LAN and Broadband Access*IEEE Trans. On Signal Processing/, May 1998

N. R. Shanbhag and G.-H. ImEnergy-efficiency in the presence of deep submicron noise

*ICCAD98*, 1998

R. Hegde and N. R. ShanbhagEfficient wireless image transmission under total power constraint

*IEEE Workshop on Multimedia Signal Processing*, 1998

S. Appadwedula, M. Goel, D. L. Jones, K. Ramchandran, and N. R. ShanbhagLow-power digital signal processing via dynamic algorithm transformations (DAT)

*Proceedings of Asilomar Conference on Signals, Systems and Computers*, November, 1998

M. Goel and N. R. ShanbhagLow-power equalizers for 51.84 Mb

*s very high-speed digital subscriber loop (VDSL) modems*Proc. of IEEE Workshop on Signal Processing Systems/, Oct. 1998

M. Goel and N. R. ShanbhagDecorrelating (DECOR) transformations for low-power adaptive filters

*Proc. of Intl. Symp. on Low-Power Electronic Design*, August 1998

S. Ramprasad, N. R. Shanbhag, and I. N. HajjLow-power reconfigurable signal processing via dynamic algorithm transformations (DAT)

*Proceedings of International Conference on Acoustics, Speech and Signal Processing*, May 1998

M. Goel and N. R. ShanbhagA Low-power VLSI design methodology for high bit-rate data communications over UTP Channel

*Proceedings of IEEE International Symposium on Circuits and Systems*, June 1998

M. Goel and N. R. ShanbhagImproving the throughput of flexible-precision DSPs via algorithm transformation

*ICASSP98*, 1998

M. Aggarwal, N. Shanbhag, N. AhujaSignal coding for low power: Fundamental limits and practical realizations

*ISCAS 98*, 1998

S. Ramprasad, N. R. Shanbhag, and I. N. HajjAnalytical expressions for average bit statistics of signal lines in DSP architectures

*ISCAS98*, 1998

S. Bobba, I. N. Hajj and N. R. ShanbhagCoding for low-power address and data busses: A source-coding framework and applications

*1998 Int. Conf. on VLSI Design*, January 1998

S. Ramprasad, N. R. Shanbhag, and I. N. Hajj

A mathematical basis for power-reduction in digital VLSI systems

*IEEE Trans. on Circuits and Systems, Part II*, Nov. 1997

N. R. ShanbhagA low-power phase-splitting adaptive equalizer for high bit-rate communications systems

*IEEE Trans. on Signal Processing*, Nov. 1997

R. Hegde and N. R. ShanbhagA pipelined strength-reduced adaptive filter : Finite-precision analysis and application to 155.52 Mb

*s ATM-LAN*1997 Proc. Midwest Symposium on Circuits and Systems/, August 1997

M. Goel and N. R. ShanbhagAnalytical estimation of signal transition activity from word-level statistics

*IEEE Trans. on CAD*, July 1997

S. Ramprasad, N. R. Shanbhag, and I. N. HajjLow-power adaptive filter architectures and their application to 51.84 Mb

*s ATM-LAN*IEEE Trans. on Signal Processing/, May 1997

N. R. Shanbhag and M. GoelAchievable bounds on signal transition activity

*ICCAD97*, 1997

S. Ramprasad, N. R. Shanbhag, and I. N. HajjDynamic algorithm transformations (DAT) for low-power adaptive signal processing

*Proc. of Intl. Symp. on Low-Power Electronic Design*, August 1997

M. Goel and N. R. ShanbhagAnalytical estimation of transition activity from word-level signal statistics

*1997 Design Automation Conference*, 1997

S. Ramprasad, N. R. Shanbhag, and I. N. HajjAnalytical Estimation of Transition Activity of DSP Architectures

*IEEE International Symposium on Circuits and Systems*, June 1997

S. Ramprasad, N. R. Shanbhag, and I. N. HajjVLSI Systems Design for 51.84 Mb

*s ATM-LAN*Proc. IEEE Intl. Symp. on Circuits and Systems/, June 1997

G.-H. Im and N. R. ShanbhagPerformance of the strength-reduced adaptive filter architecture for 51.84 Mb

*s ATM-LAN*Proc. IEEE Intl. Symp. on Circuits and Systems/, June 1997

M. Goel and N. R. Shanbhag

Pipelined adaptive IIR filter architectures using scattered and relaxed look-ahead transformations

*IEEE Trans. on Signal Processing*, July 1996

N. R. Shanbhag and G.-H. ImA fundamental basis for power-reduction in VLSI circuits

*ISCAS*1996

N. R. ShanbhagLow-power adaptive filter architectures via strength reduction

*Proc. IEEE Symp. on Low Power Electronics Design*, August 1996

M. Goel and N. R. ShanbhagLower bounds on Power-Dissipation for DSP algorithms

*Proc. IEEE Symp. on Low Power Electronics Design*, August 1996

N. R. Shanbhag

Pipelined adaptive DFE architectures using relaxed look-ahead

*IEEE Trans. on Signal Processing*, June 1995

N. R. Shanbhag and K. K. ParhiPipelined adaptive IIR filter architecture

*Proc. IEEE Intl. Symp. on Circuits and Systems*, April 1995

N. R. Shanbhag and Gi-Hong Im

An efficient design verification and test generation methodology

*AT&T Bell Labs. Technical Memorandum*, Sept. 1994

N. R. ShanbhagFinite-precision analysis of the pipelined ADPCM coder

*IEEE Trans. on Circuits and Systems*, May 1994

N. R. Shanbhag and K. K. ParhiPipelined architectures for adaptive IIR filters

*AT&T Bell Labs. Technical Memorandum*, Sept. 1994

N. R. Shanbhag and Gi-Hong ImA Pipelined VLSI NEXT Canceller for Premises Applications

*AT&T Bell Labs. Technical Memorandum*, Feb. 1994

Gi-Hong Im and N. R. ShanbhagA Pipelined VLSI NEXT Canceller for Premises Applications

*Proc. GLOBECOM ’94*, 1994

Gi-Hong Im and N. R. Shanbhag

Relaxed Look-ahead pipelined LMS adaptive filters and their application to ADPCM coder

*IEEE Trans. on Circuits and Systems*, Dec. 1993

N. R. Shanbhag and K. K. ParhiA pipelined adaptive lattice filter architecture

*IEEE Trans. on Signal Processing*, May 1993

N. R. Shanbhag and K. K. ParhiA pipelined adaptive differential vector quantizer for low-power speech coding applications

*Proc. IEEE Intl. Symp. on Circuits and Systems*, May 1993

N. R. Shanbhag and K. K. ParhiA Pipelined Kalman Filter Architecture

*Proc. 27th Asilomar Conference on Cir., Sys. and Comp.*, 1993

N. R. Shanbhag and K. K. ParhiPipelined adaptive quantizers using relaxed look-ahead

*Proc. IEEE Workshop on VLSI in Communications*, 1993

N. R. Shanbhag and K. K. ParhiPipelined adaptive DFE architectures

*SPIE Advanced Signal Processing Algorithms, Architectures, and Implementations IV*, July 1993

N. R. Shanbhag and K. K. ParhiA pipelined adaptive differential vector quantizer for low-power speech compression

*Proc. IEEE Intl. Symp. on Circuits and Systems*May 1993

N. R. Shanbhag and K. K. ParhiRoundoff error analysis of the pipelined ADPCM coder

*Proc. IEEE Intl. Symp. on Circuits and Systems*, May 1993

N. R. Shanbhag and K. K. Parhi

Some stability theorems for polygons of polynomials

*IEEE Trans. on Automatic Control*, November 1992

L. R. Pujara and N. R. ShanbhagA pipelined adaptive differential vector quantizer for real-time video compression

*Proc. IEEE Workshop on Visual Signal Processing and Communications*, Sept. 1992

N. R. Shanbhag and K. K. ParhiA pipelined adaptive lattice filter architecture: Theory and Applications

*Proc. EUSIPCO ’92*, Aug. 1992

N. R. Shanbhag and K. K. ParhiA pipelined adaptive lattice filter architecture

*Proc. IEEE Intl. Symp. on Circuits and Systems*, May 1992

N. R. Shanbhag and K. K. ParhiA high-speed architecture for ADPCM coder and decoder

*Proc. IEEE Intl. Symp on Circuits and Systems*, May 1992

N. R. Shanbhag and K. K. Parhi

An improved systolic architecture for 2-D digital filters

*IEEE Trans. on Signal Processing*, May 1991

N. R. ShanbhagA single-chip pipelined 2-D FIR filter using residue arithmetic

*IEEE Journal of Solid-State Circuits*, May 1991

N. R. Shanbhag and R. E. SiferdA pipelined LMS adaptive filter architecture

*Proc. 25th Asilomar Conf. on Sig., Sys. and Comput*, Nov. 1991

N. R. Shanbhag and K. K. ParhiThe partition of unstable polygons of polynomials

*Proc. of the American Contr. Conf.*, June 1991

L. R. Pujara and N. R. Shanbhag

Quaternary logic circuits in 2-micro CMOS technology

*IEEE Journal of Solid-State Circuits*, June 1990

N. R. Shanbhag, D. Nagchoudhuri, R. E. Siferd and G. S. VisweswaranOn the stability of polygons of polynomials with an application : An alternative proof of the edge theorem

*Proc. of the American Contr. Conf.*, May 1990

L. R. Pujara and N. R. ShanbhagA pipelined systolic 2-D FIR filter using residue arithmetic

*Proceedings of the IEEE National Aerospace and Electronics Conference*, May 1990

N. R. Shanbhag and R. E. Siferd

On the Stability of Polygon of Polynomials

*Proceedings of the Twenty-Seventh Annual Allerton Conference on Comm., Contr. and Computing*, September 1989

L. R. Pujara and N. R. Shanbhag

Parallel Implementation of a 4x4-bit multiplier using modified Booth's algorithm

*IEEE Journal of Solid-State Circuits*, Aug. 1988

N. R. Shanbhag and P. Juneja